RFW-D100 Vishay, RFW-D100 Datasheet - Page 10

• Manufacturer Part Number: RFW-D100
• Manufacturer: Vishay

Specifications of RFW-D100

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Package Type: LQFP
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

RFW-D100
Vishay RFWaves
number of clock cycles contained in each bit. This
gives the applicator the control over the bit rate with
certain restrictions. Each bit must have at least 6 clock
cycles.
The maximum bit rate is: 1 Mbps
The minimum bit rate is: 10 Kbps (TBD)
However, it is recommended to work only at 1 Mbps,
since reducing the bit rate does not change the energy
of a transmitted bit. In other words, reducing the bit rate
does not improve the bit error rate or the range
between the transmitter and the receiver.
Bit Length Register (BLR) determines the number of
clock cycles per bit (bit period).
The BLR value is given a fixed offset of 6, since the
minimum number of clock cycles in one bit is 6.
Bit Rate = Oscillator/(BLR + 6).
For example, if the input clock frequency is 12 MHz
and the wanted bit-rate is 1 Mbit/sec, then the BLR
should be set to 6 (12 / (6 + 6) = 1 Mbps). Other
examples of setting the BLR are shown in Table 2:
The RFW-D100 outputs (for the RFW122) the bit
structure shown in Figure 5.
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10
BLR REGISTER SETTING
Required Bit Rate
(Mbit/sec)
0.5
0.1
1
1
1
1
Figure 5. RFW-D100’s Bit Structure
CLOCK PERIOD
CLOCK PERIOD
Frequency (MHz)
BIT "1" STRUCTURE -
EVEN BLR VALUE
BIT "1" STRUCTURE -
RFW-D100’s
ODD BLR VALUE
BIT PERIOD
Clock
BIT PERIOD
12
18
24
12
6
1
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BLR Value
12
18
18
0
6
4
In the even clock number example, one bit contains 8
cycles of clocks and BLR=2.
In the odd clock number example, one bit contains 7
cycles of clocks and BLR=1.
The number of clocks when the line is “1” is determined
as follows:
Number of “1”s = FLOOR* ((BLR + 6)/2).
In case of “0” bit, RFW-D100 output “0” value for BLR + 6
clock pulses.
* FLOOR - Rounds towards zero
CRC
The CRC is a redundant code, which is calculated and
added to each packet on the transmitter side. The
CRC enables the receiver to detect errors in the
received packets.
The RFW-D100 adds additional CRC information to
each packet in the transmitter module, in order to
enable the protocol to detect errors. The CRC is also
calculated on the receiver side. The CRC calculation
result of the receiver and the CRC field in the received
packet are compared in the receiver by the CRC
module in the RFW-D100 (see Figure 3). If the CRC
results are equal, then the receiver knows with
reasonable probability that the packet was received
correctly. If the CRC results are not equal, then the
receiver knows with probability that the packet was
received incorrectly.
The CRC mode is configured by the PPR (3:4)
register.
Both the receiving mode and the transmitting mode in
the network have to be in the same CRC mode.
The RFW-D100 can apply CRC in three different ways:
This gives each application the flexibility to choose the
adequate amount of overhead it adds to each packet
and the corresponding level of protection that the CRC
code has.
If CRC is enabled, then the RFW-D100 calculates the
CRC of each incoming packet. It does not put the
received CRC value in the RX_FIFO. Rather, it puts
puts the result of its calculation in the RX_FIFO as the
last byte of the packet:
0x55 – CRC was received correctly.
0xAA – CRC was received incorrectly.
The status bit SSR(0) stores the result of the last
received packet.
• 16-Bit CRC – using polynomial 1 + X
• 8-Bit CRC – using polynomial 1 + X + X
• No CRC
Document Number 84675
Rev. 1.1, 22-Jan-07
2
+ X
2
+ X
15
+ X
8
16