RFW-D100 Vishay, RFW-D100 Datasheet - Page 14

• Manufacturer Part Number: RFW-D100
• Manufacturer: Vishay

Specifications of RFW-D100

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Package Type: LQFP
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

RFW-D100
Vishay RFWaves
The INT pin can be used to invoke MCU interrupts, if it
is connected to the MCU’s external interrupt pin.
There are 8 events in the RFW-D100 that can cause
the INT pin to go from low to high:
1. LOCK_IN – This interrupt indicates that the
2. LOCK_OUT – This interrupt indicates that the
3. LINK_DIS – This interrupt indicates that a “zero
4. RX_OF – This interrupt indicates that a byte from
5. TX_EMPTY – This interrupt indicates that the
www.vishay.com
14
RFW-D100 has started receiving a new packet.
The PREAMBLE has been identified. If the NET_ID
and/or the NODE_ID are enabled, then they have
been identified correctly. This event signals the
beginning of an incoming packet.
RFW-D100 has finished receiving a full packet,
including CRC. The RFW-D100 decides that it has
reached the end of a packet according to the
packet’s size. If the RFW-D100 is in fixed packet
size mode, then it has finished receiving PSR
bytes, not including CRC bytes. If the RFW-D100 is
not in fixed packet size mode, then it has finished
receiving a packet size as indicated in the packet
header. Although RX_STOP and setting TX_RX=1
(SCR2) terminate the receiving of the packet, they
do not cause a LOCK_OUT event, since the MCU
is already aware of it (the MCU initiated it). The
LOCK_OUT interrupt tells the MCU when to get
data out of the RX_FIFO.
counter” capacitor discharge event has occurred. If
a consecutive number of zero bits (according to
SCR3(4:6)) have been received, this interrupt is
set, even if zero count capacitor discharge is
disabled (SCR3(3) – EN_ZERO_DIS = ‘0’). The
actual capacitor discharge and its interrupt are two
separate mechanisms that are both invoked by the
same event, but are enabled/disabled in two
separate registers (IER(2) for the interrupt and
SCR3(3) for the discharge).
an incoming packet was discarded, since the
RX_FIFO was already full. The receiver module
(see Figure 3) tried to write a byte to a full
RX_FIFO. The MCU should know that the
corresponding packet is corrupted, since it is
lacking at least one byte.
RFW-D100 has finished transmitting a packet
normally or abnormally. Normal ending means that
all the bytes of the packet including the CRC were
transmitted. Abnormal ending means that either the
RFW-D100 has been moved to RX mode in the
middle of the packet by the MCU or the RFW-D100
For more information please contact: [e-mail]
6. RX_FIFO_AF – This interrupt indicates that
7. TX_FIFO_AE – This interrupt indicates that
CS(Carrier Sense)– This interrupt indicates that CS
All these events can be masked. If an event is masked,
then even if that event occurs, it does not set INT pin
to be “1”. The masking is done by register IER.
The reason for masking is that in different applications
or in different situations in the same application, these
events have different priorities. The MCU decides
which of these events will invoke an MCU interrupt.
PACKET SIZE
There are two types of packet structure determined by
PPR[5] (FIXED).
In both cases, the packet size does not include the
CRC addition or the PREAMBLE.
NET_ID AND NODE_ID FILTERS
NET_ID and NODE_ID are two filters in the receiver.
They filter incoming packets according to their network
address and node address.
• Fixed Sized Packet – all packets have the same,
• Variable Sized Packet – the header of the incoming
has stopped transmitting since TX_FIFO has been
empty when it should not have been. In the last
case, SRR(6) – TX_UF is also set to one.
RX_FIFO is almost full, i.e. the number of bytes in
RX_FIFO reached 12 if SCR4(3)=‘0’ or 8 if
SCR4(3)=‘1’. If the MCU does not want the
RX_FIFO to overflow, then it should empty it.
TX_FIFO is almost empty, i.e. the number of bytes
in TX_FIFO reached 4 if SCR4(3)=‘0’ or 8 if
SCR4(3)=‘1’. If the MCU did not finish putting the
transmitted packet in the TX_FIFO, then it should
continue doing so now, otherwise an underflow
event will occur.
status line has gone from “1” to “0”. This signals the
MCU that an identified or unidentified packet has
ended. Identified packet means that a PREAMBLE
has been identified. Unidentified packet means that
a PREAMBLE has not been identified. If the MCU
has a packet to transmit, and CS=”1” than the MCU
waits for this event.
fixed size. The packet size is determined in PSR
register. The packet size can be 2 ⇔ 255 bytes.
packet determines the packet size. One of the
header bytes contains the packet size. Bits
SIZE_LOC[0:1] in LCR register determines the
location (offset) of packet size inside each incoming
packet header. The RFW-D100 reads the packet
size byte in the packet header according to LCR
register.
Document Number 84675
Rev. 1.1, 22-Jan-07