WGCE5038 S L9FY Intel, WGCE5038 S L9FY Datasheet
WGCE5038 S L9FY
Specifications of WGCE5038 S L9FY
Related parts for WGCE5038 S L9FY
WGCE5038 S L9FY Summary of contents
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... Intel and the Intel logo are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Ordering Information HGCE5038 882068 WGCE5038 882129 HGCE5038 S L9F8 882067 WGCE5038 S L9FY 882071 Applications • Advanced modulation DVB-S and DSS satellite receivers requiring upgrade for DVB-S2, 8 PSK / 16 QAM ...
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... It contains a selectable RF bypass for connecting to a second receiver module. CE5038 simply requires a crystal reference and operates from supply designed as a 'simple to use' stand-alone tuner, requiring no training algorithms or user/demodulator intervention to optimize performance. The CE5038 can be used with an advanced modulation demodulator to create a highly-integrated front-end solution, operating from 1-45 MS/s. CE5038 2 Intel Corporation Data Sheet ...
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... CE5038 EEP SL CNT 11 SCL P1 12 SDA EST LOT VccLO 14 ALCAP XT VccLO 15 ADD EST PT 16 DIGDEC AGC RF 17 VccDig N VccTU DRIVE Figure 2 - Typical Application Circuit 3 Intel Corporation Data Sheet ...
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... LO Main- & Sub-Band Selection (V2:0 & S3:0 Bits 3.4.17 LO Sample Rate (LS2:0 Bits 3.4.18 LO Window Level (WS, WH2:0 & WL2:0 Bits 3.4.19 LO Window Relaxation (WRE Bit 3.4.20 LO Test (TL Bit 4.0 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1 Power-On Software Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CE5038 Table of Contents Bits Intel Corporation Data Sheet ...
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... Programming Sequence for Filter Bandwidth Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.0 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 Crystal Oscillator Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2 Absolute Maximum Ratings 6.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.4 DC Characteristics 6.5 AC Characteristics CE5038 Table of Contents 4 Intel Corporation Data Sheet ...
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... Figure 10 - Normalized Filter Transfer Characteristic (setting 20 MHz Figure 11 - Free Running LO Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12 - Copper Dimensions for Optimum Heat Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 13 - Paste Mask for Reduced Paste Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 14 - Typical Oscillator Arrangement with Optional Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 15 - Typical Arrangement for External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 CE5038 List of Figures 5 Intel Corporation Data Sheet ...
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... Table 13 - Charge Pump Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 14 - Division Ratios Set with Bits Table 15 - Frequency Bands and VCO Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table Sample Rate Data Table Window Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table Recommended Window Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 19 - Crystal Capacitor Values for 4 MHz and 10 MHz Operation CE5038 List of Tables 6 Intel Corporation Data Sheet ...
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... No. N/C 22 QOUT N/C 30 RFAGC 34 N/C 33 RFIN RFIN RFBYPASS 27 PTEST 35 RFBYPASS 28 PUMP 21 SCL 12 QDC 1 SDA 13 QDC 2 SLEEP QOUT 3 VccBB 7 Intel Corporation Data Sheet No. Name 31 RFIN 32 RFIN 33 N/C 34 RFAGC 35 PTEST 36 VccLO 37 VccLO 38 LOTEST CNT Name No. 4 VccBB 6 VccDIG 18 VccLO 36 VccLO 37 VccRF 26 VccRF 29 VccTUNE ...
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... Logic ‘0’ – normal mode. Logic ‘1’ - analogue sections are powered down. This function is OR’ed with the PD control function, see section 3.1.2. I²C serial clock input I²C serial data input/output 8 Intel Corporation Data Sheet Schematics Correction Correction Correction ...
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... Vvar In LO tuning voltage input CE5038 Function DIGDEC DIGDEC ADD ADD Input Input VccDIG VccDIG CPDEC CPDEC Vvar Vvar 9 Intel Corporation Data Sheet Schematics 400 400 XTAL XTAL 100 100 XTALCAP XTALCAP 0.2mA 0.2mA DIGDEC DIGDEC 60k 60k 20k 20k DIGDEC ...
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... Matching circuitry as per applications 32 RFIN In diagram. 33 N/C Not connected. Ground externally. 34 RFAGC In RF analogue gain control input CE5038 Function CMOS Digital Output CMOS Digital Output RFAGC RFAGC 10 Intel Corporation Data Sheet Schematics P0/P1 P0/P1 LOCK LOCK VccRF VccRF Vref Vref 5k 5k 20k 20k ...
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... Bonded to paddle. Production continuity 40 CNT test for paddle soldering Note: Exposed paddle on rear of package must be connected to GND. CE5038 Function VccLO VccLO Same configuration as pin 24 Intel Corporation Data Sheet Schematics PTEST PTEST LOTEST LOTEST Bias Bias ...
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... The input preamplifier is optimized for NF, S11 and signal handling. The signal handling of the front end is designed such that no tracking filter is required to offer immunity to input composite overload. CE5038 Figure 3 - Detailed Block Diagram 12 Intel Corporation Data Sheet ...
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... Figure 5 - Typical First Stage RF AGC Response CE5038 Figure 4 - AGC Control Structure 12.6 in 4.2 dB steps Stepped Stepped I²C bus I²C bus 1 1.5 2 2.5 3 AGC control voltage V 13 Intel Corporation Data Sheet 0 to 12.6 in 4.2 dB steps Stepped I²C bus 3.5 4 4.5 5 ...
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... MHz -10 -20 -30 -40 -50 20 Figure 7 - Variation in IIP3 with AGC Setting (RF gain adjust = +0 dB, prefilter = +4.2 dB and postfilter = 4.2 dB, baseband filter bandwidth = 22 MHz) CE5038 Gain setting Gain setting dB 14 Intel Corporation Data Sheet ...
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... The maximum output load is defined in the Electrical Characteristics Table. CE5038 -70 -60 -50 -40 -30 Input Amplitude (dBm) 15 Intel Corporation Data Sheet -20 -10 0 ...
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... Five control bits set the system reference division ratio and the baseband filter bandwidth can be programmed with a further six control bits for a nominal range MHz 1. specification compliant over the range MHz. CE5038 S11 RFBypass On S22 RFBypass On 110 150 16 0 170 que ncy ( Intel Corporation Data Sheet ...
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... For each of the three oscillators, the LO prescaler ratio (N divider ratio is automatically selected by the LO control logic, hence programming of the required conversion frequency across the oscillator bands is automatic and requires no intervention by the user. CE5038 f xtal --------- - f = -3dB BR 8MHz ) is set to ÷4 or ÷2. The required LP 17 Intel Corporation Data Sheet 1 --- - 35MHz . 3dB – ...
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... There is a further hardware lock flag (LOCK output, pin 25; see “3.1.1” on page 20) which generates a logic ‘0’ if the tuning controller detects the varactor line voltage lies within the ‘tune unlock’ window and set to logic ‘1’. In other states this output is high impedance. CE5038 100 1000 10000 Frequency offset (log (offset in kHz)) 18 Intel Corporation Data Sheet 100000 ...
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... If the controller fails to pull the SDA line low during this period, the device generates an internal STOP condition, which inhibits further reading. 1. PVR - Personal Video Recorder where dual tuners allow the viewer to watch one channel and record another simultaneously, usually to a hard-disk recording system. CE5038 19 Intel Corporation Data Sheet 1 ...
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... DIGDEC CE5038 Table 3 - Address Selection Write Address MA1 MA0 Hex. Dec 0xC0 192 0 1 0xC2 194 0xC4 196 1 1 0xC6 198 20 Intel Corporation Data Sheet Read Address Hex. Dec. 0xC1 193 0xC3 195 0xC5 197 0xC7 199 ...
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... MA1 FL SB3 SB2 SB1 SB0 Table 5 - TU1/0 Functions ‘Tune unlock’ window state Vvar between lower and upper voltage thresholds Vvar above upper voltage threshold Vvar below lower voltage threshold Undefined - do not use 21 Intel Corporation Data Sheet (LSB) MA0 1 TU1 TU0 ...
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... Register pairs may be written in any order, as required by the software, e.g., 10/11 may be followed by 4/5. Table 6 - Byte Address Allocation in Write Mode ‘X’ = Don’t care (content defines a register bit). CE5038 Data Bits Byte Selected (MSB Intel Corporation Data Sheet ...
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... LO main band select VSD LO tuning algorithm disable WH2-0 LO window high level adjust WL2-0 LO window low level adjust WRE Tuning Window Relaxation Enable WS Tuning window select 23 Intel Corporation Data Sheet 0 Reset Further information state 1 (hex.) 0 Table 3 on page 20 8 0x00 See 3.4.3 on page 24 ...
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... Table 9 - RFG Register Bit Function RFG Gain Adjust (dB Table 10 - BA1/0 Register Bits Function BA1 BA0 Pre-Filter Gain Adjust ( +12.6 Table 11 - BG1/0 Register Bits Function BG1 BG0 Post-Filter Gain Adjust ( +12.6 24 Intel Corporation Data Sheet (reset state) (reset state) (reset state) ...
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... Writing a logic ‘0’ has no effect. The following register numbers are reset to their power-on state 10, 11, 12 & 13. All other register’s contents are unaffected. CE5038 Table 12 - Port Control Bits Port state (if connected to a pull-up) High impedance 1 Low impedance to Vee (Gnd Intel Corporation Data Sheet Logic state (reset state) ...
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... Invalid Setting Division Ratios Illegal states 128 160 192 1 1 256 320 384 26 Intel Corporation Data Sheet Current limits Min. Typ. Max. ±160 ±210 ±290 ±280 ±365 ±510 ±470 ±625 ±860 ±820 ±1065 ±1470 112 224 448 ...
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... VSD bit, if required, allowing manual control. The VSD bit is programmed using byte-9, bit-7. The default is for the controller to be enabled, VSD = ‘0’, and to disable the controller a logic ‘1’ is written to this bit. CE5038 (sect. 2.4) on page 16 and “Symbol Rate and Filter 27 Intel Corporation Data Sheet ...
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... Intel Corporation Data Sheet VCO3 Min Max Kvco 1068 1081 10.0 1080 1094 10.6 1093 1108 11.2 1107 1122 11.9 ...
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... Upper WL1 WL0 Lower Lower 0 0 1.16 1. 1.64 2. 2.11 2. 2.57 2. 3.03 3. 3.49 3. 3.95 4. 4.41 4.82 Reset Values 29 Intel Corporation Data Sheet (reset state) Unlock 1 Upper 1.08 1.61 1.56 2.08 2.03 2.55 2.50 3.01 2.95 3.51 3.42 3.97 3.88 4.43 4.34 4.89 ...
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... CE5038 WH1 WH0 WL2 WL1 WL0 offs 30 Intel Corporation Data Sheet . 2 WRE Lower V Upper V 1 3.49 3.89 1 2.95 4.89 ...
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... These equations can give non-integer results so rounding must be performed. The values for BR should be rounded DOWN to the nearest integer this ensures that programmable bandwidth will not be below the desired bandwidth due to rounding. CE5038 f 35 MHz --- - + --- - . = K f xtal will not be below 575 kHz and that the maximum -------- - BR 31 Intel Corporation Data Sheet f 8MHz 35MHz . bw ...
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... This minimum time equals BR/( byte BR and f is the reference crystal frequency. xtal CE5038 ⎞ 1 – = ⎠ MHz bw ⎞ 17 1.257 – 18.02285 ⎠ 34.6 MHz bw 1 -------------- - 14.647 63 = 1.257 ⎞ 14 1.257 – 59.227 ⎠ ) seconds, where BR is the decimal value of xtal 32 Intel Corporation Data Sheet ...
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... Vee connections. The CE5038 has a fairly high power density, and if the excess heat is not efficiently removed, it will rapidly overheat beyond the 125°C limit, and affect the performance or could even cause permanent damage to the device. CE5038 33 Intel Corporation Data Sheet ...
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... Note: C12 (15 pF for 10 MHz) capacitor may be added between the crystal and Gnd if an oscillator output is required. Output is from the crystal/capacitor junction. Figure 14 - Typical Oscillator Arrangement with Optional Output Figure 15 - Typical Arrangement for External Oscillator CE5038 4 MHz 10 MHz 47 pF 100 100 pF 34 Intel Corporation Data Sheet ...
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... VccTUNE+0.3 -0.3 VccRF+0.3 -0.3 VccLO+0.3 -0.3 VccBB+0.3 -0.3 3.6 -0.3 VccDIG+0.3 -0.3 DIGDEC+0.3 20 0.5 2.0 35 Intel Corporation Data Sheet Unit Notes V w.r.t. Vee °C °C V Vcc = Vee to 5. Each output kV To Mil-std 883B method 3015 cat1 kV ...
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... Intel Corporation Data Sheet Min. Max. Unit Notes 4.75 5.25 V w.r.t. Vee -10 70 °C Units Conditions RF bypass filter b.w. mA minimum disabled mA maximum mA minimum enabled mA maximum mA disabled ...
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... Above –60 dBm operating level See Figure 8 on page Vagc = 0. Vagc = 4. AGC monotonic, Vagc from Vee to Vcc 37 Intel Corporation Data Sheet Units Conditions V On-chip 3 kohm load resistor to VccTUNE V Parallel resonant crystal mA Vee <= Vvar <= 1.7 V (on-chip varactors forward biased) µA 1.7 V <= Vvar <= Vcc mA At Vport = 0 ...
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... Figure 2 on page 2. Bypass enabled or disabled 950-2150 MHz 25 dB Single-ended to single-ended, bypass disabled -65 dBm Converter input matching as in Figure 2 on page 2. Bypass enabled or disabled 38 Intel Corporation Data Sheet Conditions all gain settings See Figure 9 on page 16, with = 75 . See Figure 9 on page 16. With ...
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... Vp-p 31.25 2000 kHz -148 dBc/Hz SSB, within loop bandwidth. Phase detector comparison frequency = 1 MHz 32767 kHz 39 Intel Corporation Data Sheet Conditions Measured either, at baseband output of 10 MHz, PLL loop bandwidth circa 15 kHz LOTEST output . Measured at LOTEST output. ...
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... Sum IM2 product from two input tones at 1.05 and 1.1 GHz at -9 dBm converted to 2150 MHz. 14. PLL loop bandwidth ~15 kHz, comparison frequency MHz. 15. Integrated rms LO jitter measured from 1 kHz to 15 MHz, PLL loop bandwidth 15 kHz. Varactor voltage = 3.5 volts. 16. RSD = 0 for 8 MHz <= fset <= 20 MHz, RSD = 1 for 20 MHz <= fset <= 35 MHz. CE5038 40 Intel Corporation Data Sheet ...