GAL18V10B-20LP Lattice, GAL18V10B-20LP Datasheet - Page 2

• Manufacturer Part Number: GAL18V10B-20LP
• Description: IC GAL 10OUT MACROCELL 7.5NS 20
• Manufacturer: Lattice
• Series: -r

Specifications of GAL18V10B-20LP

• Programmable Type: EE PLD
• Number Of Macrocells: 10
• Voltage - Input: 4.75 V ~ 5.25 V
• Speed: 20ns
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant
• Other names: Q6330552

• HIGH PERFORMANCE E
• LOW POWER CMOS
• ACTIVE PULL-UPS ON ALL PINS
• E
• TEN OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
The GAL18V10, at 7.5 ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E
PLD. CMOS circuitry allows the GAL18V10 to consume much less
power when compared to its bipolar counterparts. The E
ogy offers high speed (<100ms) erase times, providing the ability
to reprogram or reconfigure the device quickly and efficiently.
By building on the popular 22V10 architecture, the GAL18V10
eliminates the learning curve usually associated with using a new
device architecture. The generic architecture provides maximum
design flexibility by allowing the Output Logic Macrocell (OLMC)
to be configured by the user. The GAL18V10 OLMC is fully com-
patible with the OLMC in standard bipolar and CMOS 22V10 de-
vices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Copyright © 2003 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. [phone]; 1-800-LATTICE; FAX [phone]; http://www.latticesemi.com
18v10_04
Features
Description
— 7.5 ns Maximum Propagation Delay
— Fmax = 111 MHz
— 5.5 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS
— 75 mA Typical Icc
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— Uses Standard 22V10 Macrocell Architecture
— Maximum Flexibility for Complex Logic Designs
— 100% Functional Testability
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
2
CELL TECHNOLOGY
2
) floating gate technology to provide a very flexible 20-pin
®
Advanced CMOS Technology
2
CMOS
®
TECHNOLOGY
2
technol-
1
Functional Block Diagram
Pin Configuration
I
I
I
I
I
4
6
8
I/CLK
I/O/Q
I
9
I
I
I
I
I
I
I
GAL18V10
GND
2
I
PLCC
Top View
I/CLK
I/O/Q
11
High Performance E
I/O/Q I/O/Q
Vcc
20
I/O/Q
13
18
16
14
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Generic Array Logic™
GAL18V10
RESET
PRESET
10
10
8
8
8
8
8
8
8
8
I/CLK
I/O/Q
GND
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
I
I
I
I
I
I
I
November 2003
1
10
5
18V10
2
DIP
GAL
CMOS PLD
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
20
15
11
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q