GAL22V10D-15LP Lattice, GAL22V10D-15LP Datasheet - Page 15

• Manufacturer Part Number: GAL22V10D-15LP
• Description: SPLD - Simple Programmable Logic Devices 5V 22 I/O
• Manufacturer: Lattice

Specifications of GAL22V10D-15LP

• Logic Family: GAL
• Number Of Macrocells: 10
• Maximum Operating Frequency: 83.3 MHz
• Number Of Programmable I/os: 10
• Delay Time: 15 ns
• Operating Supply Voltage: 5 V
• Supply Current: 90 mA
• Maximum Operating Temperature: + 75 C
• Minimum Operating Temperature: 0 C
• Package / Case: PDIP-24
• Mounting Style: Through Hole
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Lead Free Status / Rohs Status: No

An electronic signature (ES) is provided in every GAL22V10
device. It contains 64 bits of reprogrammable memory that can
contain user-defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the se-
curity cell.
The electronic signature is an additional feature not present in
other manufacturers' 22V10 devices. To use the extra feature of
the user-programmable electronic signature it is necessary to
choose a Lattice Semiconductor 22V10 device type when com-
piling a set of logic equations. In addition, many device program-
mers have two separate selections for the device, typically a
GAL22V10 and a GAL22V10-UES (UES = User Electronic Sig-
nature) or GAL22V10-ES. This allows users to maintain compat-
ibility with existing 22V10 designs, while still having the option to
use the GAL device's extra feature.
The JEDEC map for the GAL22V10 contains the 64 extra fuses
for the electronic signature, for a total of 5892 fuses. However,
the GAL22V10 device can still be programmed with a standard
22V10 JEDEC map (5828 fuses) with any qualified device pro-
grammer.
A security cell is provided in every GAL22V10 device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the
device, so the original configuration can never be examined once
this cell is programmed. The Electronic Signature is always avail-
able to the user, regardless of the state of this control cell.
GAL22V10 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pullups
instead of the traditional p-channel pullups to eliminate any pos-
sibility of SCR induced latching.
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers (see the the GAL Development Tools section). Com-
plete programming of the device takes only a few seconds. Eras-
ing of the device is transparent to the user, and is done automati-
cally as part of the programming cycle.
Electronic Signature
Security Cell
Latch-Up Protection
Device Programming
13
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state condi-
tions.
The GAL22V10 device includes circuitry that allows each regis-
tered output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If
necessary, approved GAL programmers capable of executing test
vectors perform output register preload automatically.
GAL22V10 devices are designed with TTL level compatible in-
put buffers. These buffers have a characteristically high imped-
ance, and present a much lighter load to the driving logic than bi-
polar TTL devices.
The input and I/O pins also have built-in active pull-ups. As a re-
sult, floating inputs will float to a TTL high (logic 1). However,
Lattice Semiconductor recommends that all unused inputs and
tri-stated I/O pins be connected to an adjacent active input, Vcc,
or ground. Doing so will tend to improve noise immunity and
reduce Icc for the device. (See equivalent input and I/O schemat-
ics on the following page.)
Output Register Preload
Input Buffers
- 2 0
- 4 0
- 6 0
0
0
Specifications GAL22V10
1 . 0
Typical Input Current
In p u t V o lt ag e ( V o lt s)
2 . 0
3 . 0
4 . 0
5 . 0