CS5523-AS Cirrus Logic Inc, CS5523-AS Datasheet - Page 14

• Manufacturer Part Number: CS5523-AS
• Description: ADC (A/D Converters) 4-Ch 16-Bit Delta Sigma ADC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5523-AS

• Architecture: Delta-Sigma
• Conversion Rate: 0.617 KSPs
• Input Type: Voltage
• Maximum Power Dissipation: 500 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: No

1.1.1 Instrumentation Amplifier
The instrumentation amplifier is chopper stabilized
and is activated any time conversions are performed
with the low-level input ranges, ≤100 mV. The am-
plifier is powered from VA+ and from the NBV
(Negative
CS5521/22/23/24/28 to be operated in either of two
analog input configurations. The NBV pin can be bi-
ased to a negative voltage between -1.8 V and
-2.5 V, or tied to AGND (for the CS5528, NBV has
to be between -1.8 V and -2.5 V for the ranges below
100 mV when the amplifier is engaged). The com-
mon-mode-plus-signal range of the instrumentation
amplifier is 1.85 V to 2.65 V with NBV grounded.
The common-mode-plus-signal range of the instru-
mentation amplifier is -0.150 V to 0.950 V with
NBV between -1.8 V to -2.5 V. Whether NBV is
tied between -1.8 V and -2.5 V or tied to AGND,
the (Common Mode + Signal) input on AIN+ and
AIN- must stay between NBV and VA+.
Figure 5 illustrates an analog input model for the
ADCs when the instrumentation amplifier is en-
gaged. The CVF (sampling) input current for each
of the analog input pins depends on the CFS1 and
CFS0 (Chop Frequency Select) bits in the configu-
ration register (see Configuration Register for de-
tails). Note that the CVF current is lowest with the
14
Figure 5. Input Models for AIN+ and AIN- pins,
V
i = fV
n
o s
≤ 2 5 m V
A IN
os
2 5 m V , 55 m V , a nd 10 0 m V R a n g es
C F S 1 /C F S 0 = 00 , f = 2 5 6 H z
C F S 1 /C F S 0 = 01 , f = 4 09 6 H z
C F S 1 /C F S 0 = 10 , f = 1 6.38 4 k H z
C F S 1 /C F S 0 = 11 , f = 1 02 4 H z
C
Bias
mV Input Ranges
Voltage)
C = 48 p F
pin
allowing
≤
100
the
CFS bits in their default states (cleared to logic 0s).
Further note that the CVF current into the instru-
mentation amplifier is less than 300 pA over -40°C
to +85°C. Note that Figure 5 is for input current
modeling only. For physical input capacitance see
‘Input Capacitance’ specification under ANALOG
CHARACTERISTICS. Also refer to Applications
Note
Input Structures”
and input sampling currents.
Note: Residual noise appears in the converter’s baseband for
1.1.2 Coarse/Fine Charge Buffers
The unity gain buffers are activated any time conver-
sions are performed with the high-level inputs rang-
es, 1 V, 2.5 V, and 5 V. The unity gain buffers are
designed to accommodate rail-to-rail input signals.
The common-mode-plus-signal range for the unity
gain buffer amplifier is NBV to VA+.
Typical CVF (sampling) current for the unity gain
buffer
(XIN = 32.768 kHz, see Figure 6).
Figure 6. Input Models for AIN+ and AIN- pins,
V
i = fV
n
output word rates greater than 61.6 Sps if the CFS bits
are logic 0 (chop clock = 256 Hz). For word rates of
30 Sps and lower, 256 Sps chopping is recommended,
and for 61.6 Sps, 84.5 Sps and 101.1 Sps word rate set-
tings, 4096 Hz chopping is recommended.
AN30 - “Switched-Capacitor A/D Converter
o s
≤ 25 m V
A IN
os
amplifiers
C
1 V , 2.5 V and 5 V R anges
mV input ranges
f = 3 2 .76 8 kH z
for more details on input models
CS5521/22/23/24/28
,
φ C oa rs e
is
1
φ F in e
C = 2 0 pF
1
about
DS317F8
>
10 nA
100