CY7C09289-9AI Cypress Semiconductor Corp, CY7C09289-9AI Datasheet - Page 9

• Manufacturer Part Number: CY7C09289-9AI
• Description: SRAM Chip Sync Dual 5V 1M-Bit 64K x 16 20ns/9ns 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09289-9AI

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 1 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 5 V
• Number Of I/o Lines: 16 Bit
• Number Of Ports: 2
• Number Of Words: 64K

Switching Waveforms
Bank Select Pipelined Read
Left Port Write to Flow-Through Right Port Read
Notes:
Document #: 38-06040 Rev. *A
ADDRESS
19. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; each Bank consists of one Cypress dual-port device from this data sheet.
20. UB, LB, OE and ADS = V
21. The same waveforms apply for a right port write to flow-through left port read.
22. CE
23. OE = V
24. It t
ADDRESS
DATA
DATA
ADDRESS
ADDRESS
DATA
ADDRESS
valid until t
DATA
CE
CE
CCS
OUT(B2)
OUT(B1)
0
, UB, LB, and ADS = V
CLK
CLK
R/W
CLK
R/W
OUTR
0(B1)
0(B2)
(B1)
IL
(B2)
INL
maximum specified, then data from right port READ is not valid until the maximum specified for t
for the right port, which is being read from. OE = V
L
R
R
R
CCS
L
L
L
(B1)
= ADDRESS
+ t
t
t
t
t
SA
SC
SA
SC
CD1
. t
t
t
CWDD
t
SW
SA
SD
A
IL
A
; CE
IL
0
0
(B2)
; CE
t
does not apply in this case.
CH2
MATCH
VALID
.
1(B1)
(continued)
[19, 20]
1
, CNTEN, and CNTRST = V
t
t
t
t
SW
SA
MATCH
t
t
t
t
CYC2
, CE
CCS
HA
HC
HA
HC
t
DC
1(B2)
t
CL2
t
t
t
t
t
HW
HA
HW
HD
HA
, R/W, CNTEN, and CNTRST = V
A
A
1
1
t
CWDD
t
CD2
t
CD1
IH
t
[21, 22, 23, 24]
SC
IH
for the left port, which is being written to.
.
D
t
0
SC
A
A
2
2
t
t
DC
HC
IH
.
t
HC
t
CD2
MATCH
NO
VALID
D
MATCH
A
A
1
3
3
t
NO
DC
t
t
CKLZ
CKHZ
t
t
CD2
DC
CWDD
. If t
t
CD1
CCS
D
A
A
4
2
>maximum specified, then data is not
4
t
t
t
CKHZ
CD2
CKLZ
CY7C09279/89
CY7C09379/89
D
3
A
A
VALID
Page 9 of 18
5
t
5
CKLZ
t
t
CKHZ
CD2
D
4
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