CY7C09579V-100AC Cypress Semiconductor Corp, CY7C09579V-100AC Datasheet - Page 10

• Manufacturer Part Number: CY7C09579V-100AC
• Description: SRAM Chip Sync Dual 3.3V 1.125M-Bit 32K x 36 12.5ns/5ns 144-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09579V-100AC

• Package: 144TQFP
• Timing Type: Synchronous
• Density: 1.125 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 15 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 2
• Number Of Words: 32K

Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = V
Read Cycle for Pipelined Operation (FT/PIPE = V
Notes
Document Number: 38-06054 Rev. *E
12. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
13. ADS = V
14. The output is disabled (high-impedance state) by CE=V
15. Addresses do not have to be accessed sequentially since ADS = V
Data
Address
Data
Address
B
CLK
R/W
CLK
R/W
OUT
B
OUT
CE
0-3
OE
IL
OE
CE
0-3
, CNTEN = V
t
t
t
t
t
t
SC
SW
SA
SC
SW
SA
IL
and CNTRST = V
A
A
n
n
t
t
t
t
t
t
t
HC
HW
HA
t
CH2
HC
HW
HA
CH1
t
1 Latency
CKLZ
t
CD1
t
IH
t
CYC2
CYC1
.
t
t
CKLZ
SB
t
t
t
SB
CL2
CL1
IH
A
A
n+1
following the next rising edge of the clock.
n+1
t
Q
DC
t
HB
n
t
t
CD2
IL
HB
constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
IH
IL
)
[12, 13, 14, 15]
)
[12, 13, 14, 15]
Q
A
A
n
n+2
n+2
Q
t
OHZ
n+1
t
DC
Q
t
t
t
SC
OE
SC
t
n+1
t
OLZ
OHZ
A
A
n+3
n+3
t
OLZ
Q
t
DC
n+2
t
t
HC
HC
t
CKHZ
t
OE
CY7C09569V
CY7C09579V
Q
Page 10 of 32
n+2
[+] Feedback