CY7C09579V-100AC Cypress Semiconductor Corp, CY7C09579V-100AC Datasheet - Page 19

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CY7C09579V-100AC

Manufacturer Part Number
CY7C09579V-100AC
Description
SRAM Chip Sync Dual 3.3V 1.125M-Bit 32K x 36 12.5ns/5ns 144-Pin TQFP
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C09579V-100AC

Package
144TQFP
Timing Type
Synchronous
Density
1.125 Mb
Data Rate Architecture
SDR
Typical Operating Supply Voltage
3.3 V
Address Bus Width
15 Bit
Number Of I/o Lines
36 Bit
Number Of Ports
2
Number Of Words
32K
Switching Waveforms
Write with Address Counter Advance (Flow-Through or Pipelined Outputs)
Notes
Document Number: 38-06054 Rev. *E
57. CE= B0 = B1 = B2 = B3 = R/W = V
58. The “Internal Address” is equal to the “External Address” when ADS = CNTEN = V
Address
Address
CNTEN
Internal
Data
ADS
CLK
IN
t
t
SCN
t
SAD
t
SA
SD
D
A
Write External
n
n
t
CH2
Address
t
CYC2
t
t
IL
t
HAD
HCN
t
HA
HD
(continued)
; CNTRST = V
t
CL2
A
n
D
n+1
IH
.
Write with
Counter
D
n+1
A
Write Counter
n+1
Hold
IL
and CNTRST=V
D
n+2
IH
.
A
[57, 58]
n+2
Write with Counter
D
n+3
A
n+3
CY7C09569V
CY7C09579V
D
n+4
Page 19 of 32
A
n+4
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