CY7C4292V-15ASC Cypress Semiconductor Corp, CY7C4292V-15ASC Datasheet - Page 10

• Manufacturer Part Number: CY7C4292V-15ASC
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 128K x 9 64-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4292V-15ASC

• Package: 64TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 1.125 Mb
• Organization: 128Kx9
• Data Bus Width: 9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 70 °C

Switching Waveforms
Write Programmable Registers
Read Programmable Registers
Retransmit Timing
Notes:
23. Clocks are free-running in this case.
24. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t
25. For the synchronous PAE and PAF flags an appropriate clock cycle is necessary after t
REN/WEN
Q
WEN
REN
WCLK
D
0
LD
FL/RT
RCLK
EF/FF
0
–Q
–D
LD
15
8
t
t
CLKH
CLKH
[23, 24, 25]
(continued)
t
t
CLK
CLK
t
t
t
t
ENS
ENS
ENS
ENS
t
DS
PAE OFFSET
LSB
UNKNOWN
t
t
CLKL
CLKL
t
t
ENH
ENH
t
DH
t
A
PAE OFFSET
10
MSB
PAE OFFSET LSB
t
PRT
RTR
to update these flags.
PAF OFFSET
LSB
PAE OFFSET MSB
t
RTR
PAF OFFSET
RTR
MSB
.
PAF OFFSET
CY7C4282V
CY7C4292V
PAF OFFSET
LSB
MSB
4282V–15
4282V–16
4282V–14