ST24FC21M6TR STMicroelectronics, ST24FC21M6TR Datasheet - Page 7

• Manufacturer Part Number: ST24FC21M6TR
• Description: EEPROM Serial-I2C 1K-Bit 128 x 8 3.3V/5V 8-Pin SO N T/R
• Manufacturer: STMicroelectronics

Specifications of ST24FC21M6TR

• Package: 8SO N
• Interface Type: Serial-I2C
• Density: 1 Kb
• Maximum Operating Frequency: 0.1|0.4 MHz
• Maximum Random Access Time: 3500|900 ns
• Typical Operating Supply Voltage: 3.3|5 V
• Organization: 128x8
• Data Retention: 40 Year
• Hardware Data Protection: Yes
• Operating Temperature: -40 to 85 °C

Figure 6. Maximum R
When the ST24FC21 (or the ST24FC21B or the
ST24FW21) first switches to the I
DDC2B mode), it enters a transition state which is
functionally identical to I
ST24FC21 (or the ST24FC21B or the ST24FW21)
does not receive a valid I
START condition followed by a valid Device Select
co de (10 10XXX RW f o r ST 2 4F C 21 an d
ST24FW21; 1010000 RW for ST24FC21B), within
either 128 VCLK periods or a period of time of
t
ST24FC21 (or the ST24FC21B or the ST24FW21)
will revert to the Transmit-Only mode (VESA DDC1
mode).
If the ST24FC21 (or the ST24FC21B or the
ST24FW21) decodes a valid I
code, it will lock into I
signals applied on the VCLK input will not disturb
READ access from the ST24FC21 (or the
ST24FC21B or the ST24FW21). For WRITE ac-
cess, refer to the Signal Description paragraph.
When in the transition state, the count of VCLK
pulses and the internal 2 seconds timer are reset
by any activity on the SCL line. This means that,
after each high to low transition on SCL, the mem-
ory will re-initialise its transition state and will switch
back to Transmit-Only mode only after 128 more
VCLK pulses or after a new t
SIGNAL DESCRIPTIONS
RECOVERY
20
16
12
8
4
0
10
(approximat ely 2 seconds), the
2
C mode. Under this condition,
L
Value versus Bus Capacitance (C
2
C operation. But, if the
2
C sequence, that is a
RECOVERY
2
C Device Select
ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
2
C BUS (pF)
C mode (VESA
100
delay.
fc = 400kHz
fc = 100kHz
I
to synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to V
to act as a pull up (see Figure 6).
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to V
Transmit Only Clock (VCLK). The VCLK input pin
is used to synchronize data out when the ST24xy21
is in Transmit Only mode.
For the ST24LC21B and the ST24FC21 or
ST24FC21B Only, the VCLK offers also a Write
Enable (active high) function when the ST24LC21B
and the ST24FC21 or ST24FC21B are in I
rectional mode.
Write Control (WC). An hardware Write Control
feature (WC) is offered only on ST24LW21 and
ST24FW21 on pin 3. This feature is usefull to
protect the contents of the memory from any erro-
neous erase/write cycle. The Write Control signal
is used to enable (WC = V
the internal write protection. When unconnected,
the WC input is internally tied to V
pull-down resistor and the memory is write pro-
tected.
DEVICE OPERATION
2
C Serial Clock (SCL). The SCL input pin is used
BUS
) for an I
1000
CC
MASTER
to act as pull up (see Figure 6).
V CC
2
C Bus
SDA
SCL
IL
) or disable (WC = V
R L
SS
C BUS
by a 100k ohm
R L
AI01665
C BUS
2
C bidi-
7/22
CC
IH
)