XC3042A-7TQ144C Xilinx Inc, XC3042A-7TQ144C Datasheet - Page 4

• Manufacturer Part Number: XC3042A-7TQ144C
• Description: FPGA XC3000 Family 3K Gates 144 Cells 113MHz CMOS Technology 5V 144-Pin TQFP
• Manufacturer: Xilinx Inc

Specifications of XC3042A-7TQ144C

• Package: 144TQFP
• Family Name: XC3000
• Device System Gates: 3000
• Number Of Registers: 480
• Maximum Internal Frequency: 113 MHz
• Typical Operating Supply Voltage: 5 V
• Ram Bits: 30784
• Re-programmability Support: Yes
• Case: TQFP144
• Dc: 95+

XC3000 Series Field Programmable Gate Arrays
Detailed Functional Description
The perimeter of configurable Input/Output Blocks (IOBs)
provides a programmable interface between the internal
logic array and the device package pins. The array of Con-
figurable Logic Blocks (CLBs) performs user-specified logic
functions. The interconnect resources are programmed to
form networks, carrying logic signals among blocks, analo-
gous to printed circuit board traces connecting MSI/SSI
packages.
The block logic functions are implemented by programmed
look-up tables. Functional options are implemented by pro-
gram-controlled multiplexers. Interconnecting networks
between blocks are implemented with metal segments
joined by program-controlled pass transistors.
These FPGA functions are established by a configuration
program which is loaded into an internal, distributed array
of configuration memory cells. The configuration program
is loaded into the device at power-up and may be reloaded
on command. The FPGA includes logic and control signals
to implement automatic or passive configuration. Program
7-6
Figure 2: Field Programmable Gate Array Structure.
It consists of a perimeter of programmable I/O blocks, a core of configurable logic blocks and their interconnect resources.
These are all controlled by the distributed array of configuration program memory cells.
PWR
DN
P11
TCL
KIN
P12
P13
U61
I/O Blocks
P9
AA
BA
P8
3-State Buffers With Access
to Horizontal Long Lines
P7
AB
BB
P6
Interconnect Area
data may be either bit serial or byte parallel. The develop-
ment system generates the configuration program bit-
stream used to configure the device. The memory loading
process is independent of the user logic functions.
Configuration Memory
The static memory cell used for the configuration memory
in the Field Programmable Gate Array has been designed
specifically for high reliability and noise immunity. Integrity
of the device configuration memory based on this design is
assured even under adverse conditions. As shown in
Figure
inverters plus a pass transistor used for writing and reading
cell data. The cell is only written during configuration and
only read during readback. During normal operation, the
cell provides continuous control and the pass transistor is
off and does not affect cell stability. This is quite different
from the operation of conventional memory devices, in
which the cells are frequently read and rewritten.
3, the basic memory cell consists of two CMOS
P5
AC
P4
Configuration Memory
Configurable Logic
November 9, 1998 (Version 3.1)
Blocks
P3
AD
P2
GND
X3241
R