XC3042A-7TQ144C Xilinx Inc, XC3042A-7TQ144C Datasheet - Page 55

• Manufacturer Part Number: XC3042A-7TQ144C
• Description: FPGA XC3000 Family 3K Gates 144 Cells 113MHz CMOS Technology 5V 144-Pin TQFP
• Manufacturer: Xilinx Inc

Specifications of XC3042A-7TQ144C

• Package: 144TQFP
• Family Name: XC3000
• Device System Gates: 3000
• Number Of Registers: 480
• Maximum Internal Frequency: 113 MHz
• Typical Operating Supply Voltage: 5 V
• Ram Bits: 30784
• Re-programmability Support: Yes
• Case: TQFP144
• Dc: 95+

XC3100A IOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Propagation Delays (Input)
Set-up Time (Input)
Propagation Delays (Output)
Set-up and Hold Times (Output)
Clock
Global Reset Delays
Notes:
November 9, 1998 (Version 3.1)
Pad to Direct In (I)
Pad to Registered In (Q)
Pad to Clock (IK) set-up time
Clock (OK) to Pad (fast)
Output (O) to Pad
3-state to Pad
3-state to Pad
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
Clock High time
Clock Low time
Max. flip-flop toggle rate
RESET Pad to Registered In
RESET Pad to output pad
with latch transparent(XC3100A)Clock (IK)
to Registered In (Q)
same
same
begin hi-Z
same
active and valid (fast) (XC3100A)
same
1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads, see
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract
4. T
XAPP024. Typical slew rate limited output rise/fall times are approximately four times longer.
pull-up resistor or alternatively configured as a driven output or driven from an external source.
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is
negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized.
PID
R
, T
Description
PTG
XC3120A, XC3130A
(slew rate limited)
(fast)
(slew-rate limited)
(fast)
(slew-rate limited)
(slew -rate limited)
(slew-rate limited)
, and T
(XC3100A)
(XC3100A)
(XC3142A)
(XC3190A)
PICK
XC3142A
XC3164A
XC3190A
XC3195A
(fast)
(Q)
are 3 ns higher for XTL2 when the pin is configured as a user input.
Speed Grade
10
10
11
12
13
15
15
3
4
1
7
7
9
9
8
8
5
6
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
F
T
T
T
T
OKPO
OKPO
TSON
TSON
TSHZ
TSHZ
PICK
OOK
OKO
RPO
RPO
PTG
OPF
OPS
IKRI
IOH
CLK
PID
IOL
RRI
10.6
10.7
11.0
11.2
11.6
Min
227
4.5
2.0
2.0
0
XC3000 Series Field Programmable Gate Arrays
-4
Max
12.0
12.0
11.0
10.0
17.0
15.0
25.5
20.0
27.0
2.5
2.5
5.0
3.7
6.2
6.2
10.3
Min
270
9.4
9.5
9.7
9.9
1.6
1.6
-3
Max
11.0
10.0
15.0
13.0
21.0
17.0
23.0
2.2
2.2
4.4
3.3
9.0
5.5
5.5
9.0
Min
323
8.9
9.0
9.2
9.4
9.8
3.6
1.3
1.3
0
-2
Max
11.0
14.2
13.0
21.0
17.0
23.0
2.0
1.9
3.7
9.7
3.0
8.7
5.0
5.0
8.5
Min
323
8.0
8.1
8.3
8.5
8.9
3.2
1.3
1.3
0
-1
Max
10.0
11.5
13.0
21.0
17.0
22.0
1.7
1.7
3.4
8.4
3.0
8.0
4.5
4.5
6.5
Preliminary
Min
370
7.2
7.3
7.5
7.7
8.1
2.9
1.3
1.3
-09
Max
1.55
1.55
4.05
4.05
14.4
21.0
17.0
21.0
9.2
3.3
6.9
2.9
6.5
5.0
8.6
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7-57
7