STV0680B-001 STMicroelectronics, STV0680B-001 Datasheet - Page 20

• Manufacturer Part Number: STV0680B-001
• Description: DUAL-MODE DIGITAL CAMERA CHIPSET
• Manufacturer: STMicroelectronics

STV0680B hardware interfaces
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STV0680B hardware interfaces
STV0680B pinout
The STV0680B pinout has been carefully developed to minimise the physical size of the support
printed circuit board by facilitating placement of and electrical routing to peripheral support
components such as the SDRAM. The complete pinout and listing is shown in
Sensor interface
STV0680B uses a standard ST digital interface from the sensor, and the sensor clock input is
provided by an output from STV0680B. Designing a camera using this chipset should design as
close as possible to the reference design (
a functional ‘black box’, and no further details regarding the STV0680B-sensor interface are
required.
Memory interface
STV0680B is designed to interface to an external 16Mbit or 64Mbit SDRAM (see
SDRAM device must have a 16 bit wide data bus and operate from a 3.3V supply. Two sizes of
SDRAM memory are supported by STV0680B, 16MBits (1M x 16 bits wide) or 64MBits (4M x 16
bits wide), the memory size is auto-detected by STV0680B. STV0680B clocks the SDRAM at
6MHz, typically this is well below the figures offered by most manufacturers’ devices. Devices which
are PC66 and/or PC100 compliant are preferred. For interface wiring, see
SDRAM current consumption
For maximum system battery life while no pictures are being taken, and to assist in meeting
requirements for USB compliance, an SDRAM should be chosen with the lowest possible self
refresh current specification. For suggested SDRAM part numbers, see
In addition, the USB suspend mode current specification requires that the camera will consume no
greater than 300 A when un-tethered. Meeting this specification, which is included in the
requirements for USB compliance, assumes an SDRAM with up to approximately 250 A self-
refresh current, based on a current consumption of approximately 50 A for STV0680B+support
circuit.
SDRAM interface timing requirements
The following timing diagrams should be referred to when selecting SDRAM other than those
recommended in
Chapter 6
Version 3.4
Chapter 6
), in which case the chipset can be regarded as
STV0680B + VV6444/6410/6500
Chapter 6
Chapter 6
Chapter 6
Table 3
). The