ADSP-BF561SKBCZ600 Analog Devices Inc, ADSP-BF561SKBCZ600 Datasheet - Page 13

• Manufacturer Part Number: ADSP-BF561SKBCZ600
• Description: DSP Fixed-Point 16-Bit 600MHz 600MIPS 256-Pin CSP-BGA
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF561SKBCZ600

• Package: 256CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 600 MHz
• Ram Size: 32 KB
• Device Million Instructions Per Second: 600 MIPS

Preliminary Technical Data
CLOCK SIGNALS
The ADSP-BF561 can be clocked by an external crystal, a sine
wave input, or a buffered, shaped clock derived from an external
clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the ADSP-BF561 includes an on-chip
oscillator circuit, an external crystal may be used. The crystal
should be connected across the CLKIN and XTAL pins, with
two capacitors connected as shown in
Capacitor values are dependent on crystal type and should be
specified by the crystal manufacturer. A parallel-resonant, fun-
damental frequency, microprocessor-grade crystal should be
used.
As shown in
peripheral clock (SCLK) are derived from the input clock
(CLKIN) signal. An on-chip PLL is capable of multiplying the
CLKIN signal by a user programmable 1x to 63x multiplication
factor. The default multiplier is 10x, but it can be modified by a
software instruction sequence. On-the-fly frequency changes
can be effected by simply writing to the PLL_DIV register.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
CLKIN
REQUI RES PLL SEQUENCING
Figure
Figure 6. Frequency Modification Methods
“FI NE” ADJUSTMENT
Figure 5. External Crystal Connections
1× - 63×
PLL
6, the core clock (CCLK) and system
CLKIN
SCLK ≤ 133 MHZ
XTAL
SCLK ≤ CCLK
VCO
Figure 5
CLKOUT
“COARSE” ADJUSTMENT
× 1, 2, 4, 8
× 1:15
ON-THE-FLY
Rev. PrC | Page 13 of 52 | April 2004
CCLK
SCLK
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15.
Table 5. Example System Clock Ratios
The maximum frequency of the system clock is f
the divisor ratio must be chosen to limit the system clock fre-
quency to its maximum of f
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL[1–0] bits of the PLL_DIV regis-
ter. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown
in
fast core frequency modifications.
Table 6. Core Clock Ratios
BOOTING MODES
The ADSP-BF561 has three mechanisms (listed in
automatically loading internal L1 instruction memory after a
reset. A fourth mode is provided to execute from external mem-
ory, bypassing the boot sequence.
Table 7. Booting Modes
Signal Name
SSEL[3–0]
0001
0110
1010
Signal Name
CSEL[1–0]
00
01
10
11
BMODE1–0
00
01
10
11
Table
Table 5
6. This programmable core clock capability is useful for
illustrates typical system clock ratios:
Divider Ratio
VCO/SCLK
1:1
6:1
10:1
Divider Ratio
VCO/CCLK
1:1
2:1
4:1
8:1
Description
Execute from 16-bit external memory (Bypass
Boot ROM)
Boot from 8/16-bit flash
Reserved
Boot from SPI serial ROM (16-bit address
range)
SCLK
. The SSEL value can be changed
Example Frequency Ratios
(MHz)
VCO
100
300
500
Example Frequency Ratios
VCO
500
500
200
200
ADSP-BF561
SCLK
SCLK
CCLK
500
250
50
25
100
50
50
Table
. Note that
7) for