ADSP-BF561SKBCZ600 Analog Devices Inc, ADSP-BF561SKBCZ600 Datasheet - Page 23

• Manufacturer Part Number: ADSP-BF561SKBCZ600
• Description: DSP Fixed-Point 16-Bit 600MHz 600MIPS 256-Pin CSP-BGA
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF561SKBCZ600

• Package: 256CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 600 MHz
• Ram Size: 32 KB
• Device Million Instructions Per Second: 600 MIPS

Preliminary Technical Data
Clock and Reset Timing
Table 13
Figure
not select core/peripheral clocks in excess of 600/133 MHz.
Table 13. Clock and Reset Timing
1
2
3
4
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
Applies to bypass mode and non-bypass mode.
Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,
The figure below shows a x2 ratio between t
t
SCLK
CKIN
CKINL
CKINH
WRST
SCLK
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
BF561 Hardware Reference.
must always also be larger than t
7, combinations of CLKIN and clock multipliers must
and
Figure 7
CLKOUT
CLKIN
RESET
CLKIN Period
CLKIN Low Pulse
CLKIN High Pulse
RESET Asserted Pulsewidth Low
CLKOUT Period
describe clock and reset operations. Per
t
CKINL
C
3
C
1
LK
1
.
t
CKIN
CKIN
and t
t
CKINH
SCLK
, but the ratio has many programmable options. For more information, see the System Design chapter of the ADSP-
2
Rev. PrC | Page 23 of 52 | April 2004
Figure 7. Clock and Reset Timing
t
WRST
t
SCLKD
Min
25.0
10.0
10.0
11 t
7.5
4
CKIN
t
SCLK
Max
100.0
ADSP-BF561
Unit
ns
ns
ns
ns
ns