HMP8156ACN Intersil, HMP8156ACN Datasheet - Page 17

• Manufacturer Part Number: HMP8156ACN
• Description: NTSC/PAL Encoder 64-Pin MQFP
• Manufacturer: Intersil

Specifications of HMP8156ACN

• Package: 64MQFP
• Operating Temperature: 0 to 70 °C

The host processor may still read from and write to the
internal control registers.
Host Interfaces
Reset
The HMP8154/HMP8156A resets to its default operating
mode on power up, when the reset pin is asserted for at
least four CLK cycles, or when the software reset bit of the
host control register is set. During the reset cycle, the
encoder returns its internal registers to their reset state and
deactivates the I
I
The HMP8154/HMP8156A provides a standard I
and supports fast-mode (up to 400 Kbps) transfers. The
device acts as a slave for receiving and transmitting data
only. It will not respond to general calls or initiate a transfer.
The encoder’s slave address is either 0100 000x
SA input pin is low or 0100 001x
in the address is the I
The I
the interface is not active, SCL and SDA must be pulled high
using external 4-6kΩ pull-up resistors. The I
data timing is shown in Figures 20 and 21.
During I
address specifies the sub address, and is written into the
address register. Only the seven LSBs of the subaddress
are used; the MSB is ignored. Any remaining data bytes in
the I
beginning with the register specified by the address register.
The 7-bit address register is incremented after each data
byte in the I
within registers or reserved registers is ignored.
During I
specified by the address register is output. The address
register is incremented after each data byte in the I
cycle. Reserved bits within registers return a value of “0”.
Reserved registers return a value of 00
2
C Interface
2
2
C write cycle are written to the control registers,
C interface consists of the SDA and SCL pins. When
2
2
C write cycles, the first data byte after the slave
C read cycles, data from the control register
2
SDA
SCL
C write cycle. Data written to reserved bits
2
C interface.
CONDITION
2
C read flag.)
START
S
17
B
when it is high. (The ‘x’ bit
ADDRESS
H
1-7
.
2
C clock and
FIGURE 20. I
2
B
C interface
HMP8154, HMP8156A
when the
2
R/W
C read
8
2
C SERIAL TIMING FLOW
ACK
9
The HMP8154/HMP8156A’s operating modes are
determined by the contents of its internal registers which are
accessed via the I
written or read by the host processor at any time. However,
some of the bits and words are read only or reserved and
data written to these bits is ignored.
Table 10 lists the HMP8154/HMP8156A’s internal registers.
Their bit descriptions are listed in Tables 11-30.
SUB ADDRESS
1-7
(HEX)
07-0E
14-1F
28-2F
30-7F
00
01
02
03
04
05
06
0F
10
11
12
13
20
21
22
23
24
25
26
27
DATA
TABLE 10. CONTROL REGISTER NAMES
2
8
C interface. All internal registers may be
CONTROL REGISTER
Closed Caption_284A
Closed Caption_284B
Closed Caption_21A
Closed Caption_21B
Start H_Blank High
Start V_Blank High
Start H_Blank Low
Start V_Blank Low
Video Processing
Test and Unused
Aux Data Enable
Field Control 1
Field Control 2
Output Format
End H_Blank
End V_Blank
Input Format
Timing I/O 1
Timing I/O 2
Host Control
ACK
Product ID
Reserved
Reserved
Reserved
9
CONDITION
STOP
P
CONDITION
August 20, 2009
RESET
A0
0C
4A
7A
54
00
06
00
00
00
80
80
80
80
03
03
01
13
80H
00H
-
-
-
-
FN4343.5
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H