HMP8156ACN Intersil, HMP8156ACN Datasheet - Page 22

• Manufacturer Part Number: HMP8156ACN
• Description: NTSC/PAL Encoder 64-Pin MQFP
• Manufacturer: Intersil

Specifications of HMP8156ACN

• Package: 64MQFP
• Operating Temperature: 0 to 70 °C

NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
BIT
BIT
BIT
BIT
BIT
7-0
7-0
7-2
1-0
7-0
7-0
Line 284 Caption
Data
(Second Byte)
Assert BLANK
Output Signal
(Horizontal)
Reserved
Assert BLANK
Output Signal
(Horizontal)
Negate BLANK
Output Signal
(Horizontal)
Assert BLANK
Output Signal
(Vertical)
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
22
This register is cascaded with the closed caption_284A data register and they are read out
serially as 16 bits during line 281, 284, or 335 if line 284 captioning is enabled. Bit D0 of the
284A data register is shifted out first.
This 8-bit register is cascaded with Start H_Blank High Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1X clock cycles) at which to
start ignoring pixel data each scan line. The leading edge of HSYNC is count 020
register is ignored unless BLANK is configured as an output.
This 2-bit register is cascaded with Start H_Blank Low Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at which to
start ignoring pixel data each scan line. The leading edge of HSYNC is count 020
register is ignored unless BLANK is configured as an output.
This 8-bit register specifies the horizontal count (in 1X clock cycles) at which to start inputting
pixel data each scan line. The leading edge of HSYNC is count 000
unless BLANK is configured as an output.
This 8-bit register is cascaded with Start V_Blank High Register to form a 9-bit
start_vertical_blank register. During normal operation, it specifies the line number (n) to start
ignoring pixel input data (and what line number to start blanking the output video) each odd
field; for even fields, it occurs on line (n + 262) or (n + 313).
During SIF input mode, the register value (n) specifies the line number to start ignoring pixel
input data each noninterlaced input frame. The output video will be blanked starting on line
number (n) each odd field; for even fields, it occurs on line (n + 262) or (n + 313).
The leading edge of VSYNC at the start of an odd field is count 000
follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is
configured as an output.
TABLE 22. CLOSED CAPTION_284B DATA REGISTER
TABLE 24. START H_BLANK HIGH REGISTER
TABLE 23. START H_BLANK LOW REGISTER
TABLE 26. START V_BLANK LOW REGISTER
TABLE 25. END H_BLANK REGISTER
HMP8154, HMP8156A
SUB ADDRESS = 13
SUB ADDRESS = 20
SUB ADDRESS = 21
SUB ADDRESS = 22
SUB ADDRESS = 23
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
H
H
H
H
H
H
H
. This register is ignored
(note that this does not
H
H
. This
. This
August 20, 2009
000000
RESET
RESET
RESET
RESET
RESET
STATE
STATE
STATE
STATE
STATE
4A
7A
80
03
11
FN4343.5
H
B
H
H
H
B