A1460A-1PQ208C Actel, A1460A-1PQ208C Datasheet - Page 17

• Manufacturer Part Number: A1460A-1PQ208C
• Description: FPGA ACT 3 Family 6K Gates 848 Cells 125MHz 0.8um (CMOS) Technology 5V 208-Pin PQFP
• Manufacturer: Actel

Specifications of A1460A-1PQ208C

• Package: 208PQFP
• Family Name: ACT 3
• Device Logic Gates: 6000
• Device Logic Units: 848
• Device System Gates: 15000
• Number Of Registers: 768
• Maximum Internal Frequency: 125 MHz
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 167
• Maximum Propagation Delay Time: 2.6 ns

Active Power Component
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency dependent, a function of the logic and the external
I/O. Active power dissipation results from charging internal
chip capacitances of the interconnect, unprogrammed
antifuses, module inputs, and module outputs, plus external
capacitance due to PC board traces and load device inputs.
An additional component of the active power dissipation is
the totem-pole current in CMOS transistor pairs. The net
effect can be associated with an equivalent capacitance that
can be combined with frequency and voltage to represent
active power dissipation.
Equivalent Capacitance
The power dissipated by a CMOS circuit can be expressed by
the Equation 2.
Where:
Equivalent capacitance is calculated by measuring I
at a specified frequency and voltage for each circuit
component of interest. Measurements have been made over a
range of frequencies at a fixed value of V
capacitance is frequency independent so that the results may
be used over a wide range of operating conditions. Equivalent
capacitance values are shown below.
C
Modules (C
Input Buffers (
Output Buffers (C
Routed Array Clock Buffer Loads (C
Dedicated Clock Buffer Loads (C
I/O Clock Buffer Loads (C
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic must
be known. Equation 3 shows a piece-wise linear summation
over all components.
Power =V
+ (p * (C
+ 0.5 * (q
+ 0.5 * (q
+ (r
+ (s
EQ
2
2
C
V
F is the switching frequency in MHz.
* f
Values for Actel FPGAs
* CEQCI * f
CC
EQ
q2
is the power supply in volts.
EQO
is the equivalent capacitance expressed in pF.
1
2
CC
)
routed_Clk2
* C
* C
EQM
2 * [(m * C
+ C
EQCR
EQCR
Power (uW) = C
CEQI
)
L
s2
) * f
EQO
)
)
* f
* f
IO_Clk
p
+ 0.5 * (s
)
q1
q2
)
EQM
outputs
)
)
routed_Clk1
routed_Clk2
]
EQCI
* f
m
)
1
EQ
)
modules
*
EQCD
CEQCD
* V
+ (r
EQCR
CC
)
2
+ (n * C
1
* f
* F
)
* f
s1
q1
)
)
dedicated_Clk
routed_Clk1
CC
EQI
. Equivalent
* f
n
CC
)
10.4
inputs
active
6.7
7.2
1.6
0.7
0.9
(2)
(3)
Where:
m
n
p
q
q
r
r
s
s
C
C
C
C
C
C
C
f
f
fp
f
f
f
f
m
n
q1
q2
s1
s2
1
2
1
2
1
2
EQM
EQI
EQO
EQCR
EQCD
EQCI
L
A cceler ator Se rie s FP GAs – A CT
= Number of logic modules switching at f
= Number of input buffers switching at f
= Number of output buffers switching at f
= Number of clock loads on the first routed
= Number of clock loads on the second routed
= Fixed capacitance due to first routed array
= Fixed capacitance due to second routed array
= Fixed number of clock loads on the dedicated
= Fixed number of clock loads on the dedicated
= Equivalent capacitance of logic modules in pF
= Equivalent capacitance of input buffers in pF
= Equivalent capacitance of output buffers in
= Equivalent capacitance of routed array clock
= Equivalent capacitance of dedicated array
= Equivalent capacitance of dedicated I/O clock
= Output lead capacitance in pF
= Average logic module switching rate in MHz
= Average input buffer switching rate in MHz
= Average output buffer switching rate in MHz
= Average first routed array clock rate in MHz
= Average second routed array clock rate in
= Average dedicated array clock rate in MHz
= Average dedicated I/O clock rate in MHz
array clock
array clock
clock
clock
array clock
I/O clock
pF
in pF
clock in pF
in pF
MHz
™
3 Famil y
n
m
p
1-191