XC2VP100-6FF1704C Xilinx Inc, XC2VP100-6FF1704C Datasheet - Page 78
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XC2VP100-6FF1704C
Manufacturer Part Number
XC2VP100-6FF1704C
Description
FPGA Virtex-II Pro Family 99216 Cells 1200MHz 0.13um/90nm (CMOS) Technology 1.5V 1704-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet
1.XC2VP20-5FGG676C.pdf
(430 pages)
Specifications of XC2VP100-6FF1704C
Package
1704FCBGA
Family Name
Virtex-II Pro
Device Logic Units
99216
Number Of Registers
88192
Maximum Internal Frequency
1200 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
1040
Ram Bits
8183808
Re-programmability Support
Yes
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LVDS DC Specifications (LVDS_25)
Table 8: LVDS DC Specifications
Extended LVDS DC Specifications (LVDSEXT_25)
Table 9: Extended LVDS DC Specifications
LVPECL DC Specifications (LVPECL_25)
These values are valid when driving a 100 Ω differential
load only, i.e., a 100 Ω resistor between the two receiver
pins. The V
levels and are compatible with devices tolerant of lower
Table 10: LVPECL DC Specifications
DS083 (v4.7) November 5, 2007
Product Specification
Supply Voltage
Output High Voltage for Q and Q
Output Low Voltage for Q and Q
Differential Output Voltage (Q – Q),
Q = High (Q – Q), Q = High
Output Common-Mode Voltage
Differential Input Voltage (Q – Q),
Q = High (Q – Q), Q = High
Input Common-Mode Voltage
Supply Voltage
Output High Voltage for Q and Q
Output Low Voltage for Q and Q
Differential Output Voltage (Q – Q),
Q = High (Q – Q), Q = High
Output Common-Mode Voltage
Differential Input Voltage (Q – Q),
Q = High (Q – Q), Q = High
Input Common-Mode Voltage
V
V
V
Differential Input Voltage
V
OH
OL
IH
IL
DC Parameter
OH
DC Parameter
DC Parameter
R
levels are 200 mV below standard LVPECL
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
0.565
0.100
1.35
Min
0.8
0.5
V
Symbol
Symbol
CCO
V
V
V
V
V
V
V
V
V
V
V
V
V
ODIFF
V
ODIFF
IDIFF
IDIFF
CCO
OCM
CCO
OCM
ICM
ICM
OH
OH
OL
OL
= 2.375V
1.495
0.755
R
R
R
R
Common-mode input voltage = 1.25V
Differential input voltage = ±350 mV
R
R
R
R
Common-mode input voltage = 1.25V
Differential input voltage = ±350 mV
Max
2.0
1.7
1.5
T
T
T
T
T
T
T
T
= 100 Ω across Q and Q signals
= 100 Ω across Q and Q signals
= 100 Ω across Q and Q signals
= 100 Ω across Q and Q signals
= 100 Ω across Q and Q signals
= 100 Ω across Q and Q signals
= 100 Ω across Q and Q signals
= 100 Ω across Q and Q signals
www.xilinx.com
1.475
0.100
0.69
Min
0.8
0.5
Conditions
Conditions
common-mode ranges.
specifications of LVPECL. For more information on using
LVPECL
V
CCO
= 2.5V
,
see the Virtex-II Pro Platform FPGA User Guide.
Max
1.62
0.88
2.0
1.7
1.5
0.815
0.100
Table 10
Min
1.6
0.8
0.5
V
CCO
0.898
1.125
0.715
1.125
2.38
2.38
Min
247
100
Min
440
100
0.3
0.3
= 2.625V
summarizes the DC output
1.250
1.250
1.745
1.005
Max
Typ
350
350
Typ
2.5
1.2
2.5
1.2
1.5
2.0
1.7
1.602
1.375
1.785
1.375
1000
Max
2.63
Max
2.63
454
600
820
2.2
2.2
Module 3 of 4
Units
V
V
V
V
V
Units
Units
mV
mV
mV
mV
V
V
V
V
V
V
V
V
V
V
7
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