XC2VP100-6FF1704C Xilinx Inc, XC2VP100-6FF1704C Datasheet - Page 87
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XC2VP100-6FF1704C
Manufacturer Part Number
XC2VP100-6FF1704C
Description
FPGA Virtex-II Pro Family 99216 Cells 1200MHz 0.13um/90nm (CMOS) Technology 1.5V 1704-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet
1.XC2VP20-5FGG676C.pdf
(430 pages)
Specifications of XC2VP100-6FF1704C
Package
1704FCBGA
Family Name
Virtex-II Pro
Device Logic Units
99216
Number Of Registers
88192
Maximum Internal Frequency
1200 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
1040
Ram Bits
8183808
Re-programmability Support
Yes
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Table 25: RocketIO Receiver Switching Characteristics
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1.
2.
3.
4.
Receive total jitter tolerance
Receive deterministic jitter tolerance
Receive latency
RXUSRCLK duty cycle
RXUSRCLK2 duty cycle
UI = Unit Interval
The oversampling techniques described in
Receive latency delay RXP/RXN to RXDATA. Refer to
This maximum may occur when certain conditions are present and clock correction and channel bonding are enabled. If these functions are both
disabled, the maximum will be near the typical values.
RXDATA[16:0]
RXUSRCLK2
Description
RXP/RXN
R
(3)
DATA ORIGINATES
0
1
2
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
. . . . .
Figure 4: RocketIO Receive Latency (Maximum)
Symbol
T
T
T
T
XAPP572
T
RX2DC
DJTOL
RXLAT
RXDC
JTOL
20
are required to meet these specifications for serial rates less than 1 Gb/s.
RocketIO Transceiver User Guide
1.0626 Gb/s – 2.125 Gb/s
1.0626 Gb/s – 2.125 Gb/s
1
2.126 Gb/s – 3.125 Gb/s
2.126 Gb/s – 3.125 Gb/s
1.0 Gb/s – 1.0625 Gb/s
1.0 Gb/s – 1.0625 Gb/s
21 22
600 Mb/s – 999 Mb/s
600 Mb/s – 999 Mb/s
www.xilinx.com
Conditions
T
RXLAT
. . . . .
820
821 822
41
for more information on calculating latency.
Min
45
45
. . . . .
Typ
25
50
50
840 841 842
Max
0.68
0.47
0.65
0.65
0.68
0.41
0.43
0.47
42
55
55
42
DATA ARRIVES
(4)
(2)
(2)
DS083-3_02_082301
RXUSRCLK cycles
. . . .
Units
Module 3 of 4
UI
UI
UI
UI
UI
UI
UI
%
%
(1)
16
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