MT90870AG Zarlink, MT90870AG Datasheet - Page 14

• Manufacturer Part Number: MT90870AG
• Description: Switch Fabric 12K x 12K/8K x 4K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90870AG

• Package: 272BGA
• Number Of Ports: 32
• Fabric Size: 12K x 12K|8K x 4K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 2.048|4.096|8.192|16.384 Mbps
• Operating Supply Voltage: 1.8|3.3 V

Pin Description (continued)
BCSTo0-3
FP8i
C8i
CS
DS
R/W
A0 - A14
Name
C14, A15, B15,
C15
U14
W12
B11
A11
C11
C7, B7, C8, B8,
A8, D9, B9, A9,
D10, C10, A10
D5, C6, A6, D7,
Coordinates
Package
Backplane Output Channel High Impedance Control (5 V Tolerant
Three-state Outputs). Active high output enable which may be used to
control external buffering individually for a set of Backplane output
streams on a per channel basis.
In non-32 Mb/s mode (stream rates 2 Mb/s to 16 Mb/s):
BCSTo0 is the output enable for BSTo[0,4,8,12,16,20,24,28],
BCSTo1 is the output enable for BSTo[1,5,9,13,17,21,25,29],
BCSTo2 is the output enable for BSTo[2,6,10,14,18,22,26,30],
BCSTo3 is the output enable for BSTo[3,7,11,15,19,23,27,31].
In 32 Mb/s mode (stream rate 32 Mb/s):
BCSTo0 is the output enable for BSTo[0,4,8,12],
BCSTo1 is the output enable for BSTo[1,5,9,13],
BCSTo2 is the output enable for BSTo[2,6,10,14],
BCSTo3 is the output enable for BSTo[3,7,11,15].
Refer to descriptions of the BORS and ODE pins for control of the output
High or High-Impedance state.
Frame Pulse Input (5 V Tolerant). This pin accepts the Frame Pulse
signal. The pulse width may be active for 122 ns or 244 ns at the frame
boundary and the Frame Pulse Width bit (FPW) of the Control Register
must be set Low (default) for a 122 ns and set High for a the 244 ns pulse
condition.The device will automatically detect whether an ST-BUS or GCI-
BUS style frame pulse is applied.
Master Clock Input (5 V Tolerant). This pin accepts a 8.192 MHz clock.
The internal Frame Boundary is aligned with the rising edge of this clock.
This rising edge frame boundary alignment is controlled by the C8IPOL bit
in the Control Register as shown in Table 16 on page 52. The C8IPOL bit
MUST be set to ONE for the rising edge frame boundary to be detected
correctly. Falling C8i edge frame boundary alignment is not supported
and should not be used.
Chip Select (5 V Tolerant). Active low input used by the microprocessor
to enable the microprocessor port access. This input is internally set low
during a device RESET.
Data Strobe (5 V Tolerant). This active low input works in conjunction
with CS to enable the microprocessor port read and write operations.
Read/Write (5 V Tolerant). This input controls the direction of the data
bus lines (D0-D15) during a microprocessor access.
Address 0 - 14 (5 V Tolerant). These pins form the 15-bit address bus to
the internal memories and registers. (Address A0 = LSB).
Zarlink Semiconductor Inc.
MT90870
14
Description
Data Sheet