MT90870AG Zarlink, MT90870AG Datasheet - Page 58

• Manufacturer Part Number: MT90870AG
• Description: Switch Fabric 12K x 12K/8K x 4K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90870AG

• Package: 272BGA
• Number Of Ports: 32
• Fabric Size: 12K x 12K|8K x 4K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 2.048|4.096|8.192|16.384 Mbps
• Operating Supply Voltage: 1.8|3.3 V

13.5
Address 0023h to 0032h.
Sixteen Local input delay registers (LIDR0 to LIDR15) allow users to program the input bit delay for the Local input
data streams LSTi0-15. The possible adjustment is up to 7 3/4 of the data rate, advancing forward with a resolution
of 1/4 of the data rate. The data rate can be either 2 Mb/s, 4 Mb/s, 8 Mb/s or 16 Mb/s.
The LIDR0 to LIDR15 registers are configured as follows:
13.5.1
These five bits define the delay from the bit boundary that the receiver uses to sample each input. Input bit delay
adjustment can range up to 7
This can be described as: LIDn(4:0) = (no. of bits delay) / 4
For example, if LIDn(4:0) is set to 10011 (19), the input bit delay = 19 *
Table 22, Local Input Bit Delay Programming Table, illustrates the bit delay selection.
LIDRn Bit
(where n = 0
to 15)
15-5
4-0
0 (Default)
Data Rate
Local Input Bit Delay Registers (LIDR0 to LIDR15)
1 1/4
1 1/2
1 3/4
2 1/4
2 1/2
2 3/4
3 1/4
3 1/2
3 3/4
1/4
1/2
3/4
Local Input Delay Bits 4-0 (LID4 - LID0)
1
2
3
Reserved
LIDn(4:0)
Name
Table 21 - Local Channel Delay Register (LIDRn) Bits
Table 22 - Local Input Bit Delay Programming Table
3
LID4
/
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
bit periods forward, with resolution of
Reset
0
0
Zarlink Semiconductor Inc.
LID3
Reserved
Local Input Bit Delay Register
The binary value of these bits refers to the input bit delay value
for the Local input stream
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MT90870
Corresponding Delay Bits
58
LID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
/
1
4
/
4
bit period.
Description
= 4
3
/
4.
LID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Data Sheet
LID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1