MT9092AP Zarlink, MT9092AP Datasheet - Page 15

• Manufacturer Part Number: MT9092AP
• Description: Digital Telephone 44-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT9092AP

• Package: 44PLCC
• Power Supply Type: Analog
• Typical Supply Current: 8 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

Receive Interrupts
The HDLC Interrupt Enable Register (address 06h) is used to select (unmask) only those interrupts which are
deemed important to the microprocessor. After a PWRST or software RST all enable bits will be cleared causing all
interrupts to be masked.
All selected interrupt events will cause the IRQ pin to become active. Unselected interrupt events will not cause IRQ
to become active however, the event will still be represented by the appropriate bit in the HDLC Interrupt Status
Register (address 07h). This register must be read after receiving an IRQ or may be polled at any time. The IRQ
output pin is reset coincident with the first SCLK falling edge following a Command/Address byte which indicates a
microport read of address 07h. Since all interrupts are generated by the occurrence of an HDLC event (i.e., a
transition), this register informs that an event has occurred but does not guarantee that it is still valid. To determine
current validity the HDLC Status Register (address 04h) should be read. Due to the asynchronous nature of the
interrupts an interrupt occurring during a read of the Interrupt Status register will be held until the read cycle is over,
unless it is an interrupt which is already valid.
There are six interrupts associated with the receiver.
GA
EOPD
EopR
FA
RxFf - Receive FIFO filling:
RxOvfl - Receive FIFO Overflow:
Disabling, Reset and Transparent Operation
Disabling of the receiver via the HRxEn bit will occur after the current packet is completely loaded into the Rx FIFO.
Disabling can occur during packet reception if no bytes have been written to the Rx FIFO yet. The Rx FIFO, status
and Interrupt registers may still be read and control registers written while the receiver is disabled. Note that the
receiver requires the reception of a flag before processing a packet, thus if the receiver is enabled in the middle of
an incoming packet it will ignore that packet and wait for the next complete one.
Go Ahead:
End Of Packet Detect:
End of packet Read:
Frame Abort:
Set when a go-ahead pattern (011111110) has been detected by the receiver.
Set when an end of packet byte has been written into the Rx FIFO by the receiver. This event
may be due to receiving a closing flag, an abort sequence or an invalid packet.
Set when the next byte to be read from the Rx FIFO is the last byte of a packet or when a read to
an empty Rx FIFO has occurred.
Set when a frame abort sequence is received during packet reception. The aborted packet must
contain a minimum of 26 bits for the FA sequence to be recognized.
position is shared with the transmitter under-run (Txunder) interrupt (see transmit interrupts). For
this bit to reflect FA the Intsel bit in Control Register 2 (address 05h) must be set low.
Set when a transition from 14 to 15 bytes in the Rx FIFO has occurred. This is an early warning to
the microprocessor that the FIFO is filling and should be serviced before it becomes completely
full; a condition which may result in a receive overflow condition. By setting the Flrx bit (address
05h) high the FIFO filling condition will occur when a transition from 4 to 5 bytes occurs. This will
allow the microport more time to react to this interrupt condition.
Set when the receiver attempts to write data into an already full Rx FIFO. Under this condition the
HDLC will disable the receiver until a new flag is detected. See also Receive FIFO Status.
Zarlink Semiconductor Inc.
MT9092
15
Note that this register bit
Data Sheet