MT9092AP Zarlink, MT9092AP Datasheet - Page 27

• Manufacturer Part Number: MT9092AP
• Description: Digital Telephone 44-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT9092AP

• Package: 44PLCC
• Power Supply Type: Analog
• Typical Supply Current: 8 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

Note: Bits marked "-" are reserved bits and should be written with logic "0".
HDLC Interrupt Status Register
FCODEC Gain Control Register 1
This register indicates the source of an interrupt. It is used in conjunction with the Interrupt Enable Register to generate an interrupt. The register is
reset by the microprocessor read, which also resets the IRQ output. All interrupts are generated by a transition. That is, the register informs the user
that an interrupt did occur but may not presently be valid. To determine if the interrupt is presently valid the Status Register should be polled. Due to
the asynchronous nature of the interrupts, an interrupt occurring during a read of this register will be saved until the read is over, unless it is an inter-
rupt that has already been set.
GA
EOPD
TEOP
EOPR
TxFL
FA:TxUnder
RxFf
RxOvfl
Receive Gain
Setting (dB)
(default)
RxFG
-1
-2
-3
-4
-5
-6
-7
Indicates a go-ahead pattern (011111110) was detected by the HDLC receiver.
This bit is set when an end of a packet (EOP) byte is written into the RX FIFO by the HDLC receiver. This can be in the form of a
This bit is set when the transmitter has finished sending the closing flag of a packet or after a packet has been aborted .
This bit is set when the byte about to be read from the Rx FIFO is the last byte of the packet. It is also set if the Rx FIFO is read and
Tx FIFO low indication. Indicates that a transition from 5 to 4 bytes in the Tx FIFO was detected. If Fltx is set then this will be 15 to
When Intsel bit of Control Register 2 is low this bit (FA) is set when a frame abort is received during packet reception. It must be
Indicates that a transition from 14 to 15 bytes in the FIFO was detected. If Flrx is set then this will be 4 to 5 bytes.
Indicates that the Rx FIFO overflowed (i.e. an attempt to write to a full RX FIFO). The HDLC will always disable the receiver once
flag, an abort sequence, or an invalid packet.
there is no data in it.
14 bytes.
received after a minimum number of bits have been received (26) otherwise it is ignored (see HDLC FRAME STRUCTURE). When
Intsel is high this bit is set for a Tx FIFO underrun indication. Indicates that a read by the transmitter was attempted on an empty Tx
FIFO without an EOP or FA tagged byte.
the receive overflow has been detected. The receiver will be re-enabled upon detection of the next flag, but will overflow again if the
GA
-
0
7
7
n
= Receive Filter Gain n
RxFG
EOPD
6
6
RxFG
2
0
0
0
0
1
1
1
1
RxFG
TEOP EOPR
2
5
5
1
RxFG
RxFG
0
0
1
1
0
0
1
1
1
4
4
0
Zarlink Semiconductor Inc.
RxFG
TxFL
0
1
0
1
0
1
0
1
-
3
3
0
MT9092
Under
FA/Tx
TxFG
27
2
2
2
Transmit Gain
Setting (dB)
TxFG
(default) 0
RxFf
1
1
TxFG
1
2
3
4
5
6
7
1
TxFG
ADDRESS = 0Ah WRITE/READ VERIFY
n
Ovfl
Rx
= Transmit Filter Gain n
0
0
ADDRESS = 08h and 09h are RESERVED
0
TxFG
0
0
0
0
1
1
1
1
2
ADDRESS = 07h READ
TxFG
Power Reset Value
Power Reset Value
0
0
1
1
0
0
1
1
X000 X000
0000 0000
1
Data Sheet
TxFG
0
1
0
1
0
1
0
1
0