PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 7

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

7
8
9
10
11
12
13
14
15
16
17
10.1
10.2
10.3
13.1
13.2
13.3
13.4
13.5
15.1
15.2
15.3
6.3.121
6.3.122
6.3.123
6.3.124
6.3.125
6.3.126
6.3.127
6.3.128
6.3.129
6.3.130
6.3.131
6.3.132
6.3.133
GPIO PINS AND SM BUS ADDRESS....................................................................................... 64
CLOCK SCHEME ....................................................................................................................... 65
INTERRUPTS .............................................................................................................................. 67
EEPROM (I2C) INTERFACE AND SYSTEM MANAGEMENT BUS................................. 68
HOT PLUG OPERATION.......................................................................................................... 70
RESET SCHEME......................................................................................................................... 71
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER ............................................................. 72
POWER MANAGEMENT.......................................................................................................... 73
ELECTRICAL AND TIMING SPECIFICATIONS ................................................................ 75
PACKAGE INFORMATION ..................................................................................................... 77
ORDERING INFORMATION ................................................................................................... 78
Pericom Semiconductor - Confidential
EEPROM (I2C) INTERFACE ............................................................................................... 68
SYSTEM MANAGEMENT BUS.......................................................................................... 68
EEPROM AUTOLOAD CONFIGURATION ....................................................................... 69
INSTRUCTION REGISTER.................................................................................................. 72
BYPASS REGISTER ............................................................................................................. 72
DEVICE ID REGISTER ........................................................................................................ 73
BOUNDARY SCAN REGISTER.......................................................................................... 73
JTAG BOUNDARY SCAN REGISTER ORDER................................................................. 73
ABSOLUTE MAXIMUM RATINGS ................................................................................... 75
DC SPECIFICATIONS .......................................................................................................... 75
AC SPECIFICATIONS .......................................................................................................... 76
NEXT CAPABILITY OFFSET REGISTER – OFFSET 150h ................................................................ 62
PORT VC CAPABILITY REGISTER 1 – OFFSET 154h ...................................................................... 62
PORT VC CAPABILITY REGISTER 2 – OFFSET 158h ...................................................................... 62
PORT VC CONTROL REGISTER – OFFSET 15Ch............................................................................. 62
PORT VC STATUS REGISTER – OFFSET 15Ch................................................................................. 62
VC0 RESOURCE CAPABILITY REGISTER – OFFSET 160h ............................................................. 62
VC0 RESOURCE CONTROL REGISTER – OFFSET 164h ................................................................. 62
VC0 RESOURCE STATUS REGISTER – OFFSET 168h ..................................................................... 63
RESERVED REGISTERS – OFFSET 16Ch – 300h .............................................................................. 63
EXTRA GPI/GPO DATA AND CONTROL REGISTER – OFFSET 304h............................................. 63
RESERVED REGISTERS – OFFSET 308h – 30Ch .............................................................................. 63
REPLAY AND ACKNOWLEDGE LATENCY TIMERS – OFFSET 310h ............................................. 63
RESERVED REGISTERS – OFFSET 314h – FFCh ............................................................................. 63
Page 7 of 78
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL