ISL23348UFVZ Intersil, ISL23348UFVZ Datasheet

ISL23348UFVZ

Manufacturer Part Number

ISL23348UFVZ

Description

IC DGTL POT 4CH 50K 20TSSOP

Manufacturer

Intersil

Series

XDCP™r

Datasheet

1.ISL23348WFVZ-TK.pdf (19 pages)

Specifications of ISL23348UFVZ

Taps

128

Resistance (ohms)

50K

Number Of Circuits

Temperature Coefficient

65 ppm/°C Typical

Memory Type

Volatile

Interface

I²C (Device Address)

Voltage - Supply

1.2 V ~ 5.5 V, 1.7 V ~ 5.5 V

Operating Temperature

-40°C ~ 125°C

Mounting Type

Package / Case

Lead Free Status / Rohs Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

ISL23348UFVZ-T7A

Manufacturer:

Intersil

Quantity:

500

Current page: 1 of 19
Download datasheet (860Kb)

Quad, 128 Tap, Low Voltage Digitally Controlled

Potentiometer (XDCP™)

ISL23348

The ISL23348 is a volatile, low voltage, low noise, low power,

128 tap, quad digitally controlled potentiometer (DCP) with an

switches and control logic on a monolithic CMOS integrated

circuit.

Each digitally controlled potentiometer is implemented with a

combination of resistor elements and CMOS switches. The

position of the wipers are controlled by the user through the

volatile Wiper Register (WRi, i = 0, 1, 2, 3) that can be directly

written to and read by the user. The contents of the WRi

controls the position of the wiper. When powered on, the wiper

of each DCP will always commence at mid-scale (64 tap

position).

The low voltage, low power consumption, and small package

of the ISL23348 make it an ideal choice for use in battery

operated equipment. In addition, the ISL23348 has a V

pin allowing down to 1.2V bus operation, independent from the

directly to the ISL23348 without passing through a voltage

level shifter.

The DCP can be used as a three-terminal potentiometer or as a

two-terminal variable resistor in a wide variety of applications

including control, parameter adjustments, and signal processing.

Applications

• Power supply margining

• Trimming sensor circuits

• Gain adjustment in battery powered instruments

• RF power amplifier bias compensation

August 24, 2011

FN7903.1

C Bus™ interface. It integrates four DCP cores, wiper

C bus interface. Each potentiometer has an associated

10000

FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP

value. This allows for low logic levels to be connected

8000

6000

4000

2000

POSITION, 10kΩ DCP

TAP POSITION (DECIMAL)

LOGIC

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.

1-888-INTERSIL or 1-888-468-3774

128

Features

• Four potentiometers per package

• 128 resistor taps

• 10kΩ, 50kΩ or 100kΩ total resistance

• I

• Maximum supply current without serial bus activity

• Shutdown mode

• Power supply

• Wiper resistance: 70Ω typical @ V

• Power-on preset to mid-scale (64 tap position)

• Extended industrial temperature range: -40

• 20 Ld TSSOP or 20 QFN packages

• Pb-free (RoHS compliant)

- No additional level translator for low bus supply

- Three address pins allow up to eight devices per bus

(standby)

- 5µA @ V

- 2µA @ V

- Forces the DCP into an end-to-end open circuit and RWi is

- Reduces power consumption by disconnecting the DCP

- V

ISL23348

C serial interface

1 DCP

connected to RLi internally

resistor from the circuit

All other trademarks mentioned are the property of their respective owners

LOGIC

= 1.7V to 5.5V analog power supply

= 1.2V to 5.5V I

REF

RH1

RL1

FIGURE 2. V

and V

RW1

LOGIC

= 5V

= 1.7V

REF

C bus/logic power supply

ADJUSTMENT

ISL28114

= 3.3V

C to +125

REF_M

Related parts for ISL23348UFVZ

ISL23348UFVZ Summary of contents

Page 1

... FIGURE 2. V CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners = 5V LOGIC = 1.7V ...

Page 2

Block Diagram V LOGIC SCL SDA I/O A0 BLOCK A1 A2 Pin Configurations ISL23348 (20 LD TSSOP) TOP VIEW RL0 1 RW0 RH0 4 RL1 5 RW1 6 RH1 7 GND LOGIC 10 ...

Page 3

... Ordering Information PART NUMBER (Notes PART MARKING ISL23348TFVZ 23348 TFVZ ISL23348UFVZ 23348 UFVZ ISL23348WFVZ 23348 WFVZ ISL23348TFRZ 348T ISL23348UFRZ 348U ISL23348WFRZ 348W NOTES: 1. Add “-TK” suffix for 1k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to 2 ...

Page 4

... Thermal Resistance (Typical TSSOP Package (Notes QFN Package (Notes Maximum Junction Temperature (Plastic Package .+150°C Storage Temperature Range .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C V Supply Voltage 1. Supply Voltage ...

Page 5

Analog Specifications V = 2.7V to 5.5V Boldface limits apply over the operating temperature range, -40°C to +125°C. SYMBOL PARAMETER VOLTAGE DIVIDER MODE ( RH; measured at RW, unloaded) CC INL Integral Non-linearity, Guaranteed ...

Page 6

Analog Specifications V = 2.7V to 5.5V Boldface limits apply over the operating temperature range, -40°C to +125°C. SYMBOL PARAMETER R Offset, Wiper at 0 Position offset (Note 16) Rmatch DCP to DCP Matching (Note 23) TCR Resistance ...

Page 7

Operating Specifications Boldface limits apply over the operating temperature range, -40°C to +125°C. SYMBOL PARAMETER t Wiper Response Time DCP tShdnRec DCP Recall Time from Shutdown Mode Ramp Rate CC, LOGIC CC , LOGIC Ramp (Note ...

Page 8

Serial Interface Specification SYMBOL PARAMETER t STOP Condition Set-up Time SU:STO t STOP Condition Hold Time for Read HD:STO or Write t Output Data Hold Time DH t SDA and SCL Rise Time R t SDA and SCL Fall Time ...

Page 9

DCP Macro Model Timing Diagrams SDA vs SCL Timing SCL t SU:STA t HD:STA SDA (INPUT TIMING) SDA (OUTPUT TIMING) A0, A1 and A2 Pin Timing START SCL SDA A0, A1 ISL23348 R TOTAL ...

Page 10

Typical Performance Curves 0.15 0.10 0.05 0.00 -0.05 -0.10 -0. TAP POSITION (DECIMAL) FIGURE 3. 10kΩ DNL vs TAP POSITION, V 0.15 0.10 0.05 0.00 -0.05 -0.10 -0. TAP POSITION (DECIMAL) FIGURE 5. 10kΩ ...

Page 11

Typical Performance Curves 0.30 0.25 0.20 0.15 0.10 0.05 0. TAP POSITION (DECIMAL) FIGURE 9. 10kΩ RINL vs TAP POSITION, V 100 +25° -40° TAP POSITION (DECIMAL) FIGURE 11. ...

Page 12

Typical Performance Curves 400 300 200 100 TAP POSITION (DECIMAL) FIGURE 15. 10kΩ TCr vs TAP POSITION TAP POSITION (DECIMAL) FIGURE 17. 100kΩ TCv vs TAP POSITION, V ...

Page 13

Typical Performance Curves 1V/DIV 0.2µs/DIV SCL 9TH CLOCK OF THE FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME CH1: RH TERMINAL CH2: RW TERMINAL 0.5V/DIV, 0.2µs/DIV -3dB FREQUENCY = 1.437MHz AT MIDDLE TAP FIGURE 23. 10kΩ -3dB CUT OFF FREQUENCY Functional ...

Page 14

ISL23348. A maximum of eight ISL23348 devices may occupy the I bus (see Table 3). V LOGIC Digital power source for the logic control section. It supplies an internal level translator for ...

Page 15

POWER-UP MID SCALE = 80H USER PROGRAMMED SHDN ACTIVATED SHDN RELEASED SHDN MODE 0 TIME (s) FIGURE 26. SHUTDOWN MODE WIPER RESPONSE Serial Interface 2 The ISL23348 supports bidirectional bus oriented protocol. The protocol ...

Page 16

SCL FROM MASTER SDA OUTPUT FROM TRANSMITTER SDA OUTPUT FROM RECEIVER START SIGNALS FROM THE MASTER SIGNAL AT SDA SIGNALS FROM THE SLAVE S SIGNALS T FROM THE A IDENTIFICATION MASTER R BYTE WITH T R SIGNAL AT ...

Page 17

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. ...

Page 18

Package Outline Drawing M20.173 20 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 2, 5/10 1 6.50 ±0.10 20 6.40 4.40 ±0. 0. TOP VIEW H C SEATING PLANE 0.10 C SIDE VIEW (5.65) ...

Page 19

Package Outline Drawing L20.3x4 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 3/10 3. PIN 1 INDEX AREA A TOP VIEW (2.65) (3.80) (1.65) (2.80) TYPICAL RECOMMENDED LAND PATTERN 19 ISL23348 A B 20X 4 4.00 0.15 ...

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