ISL23348UFVZ Intersil, ISL23348UFVZ Datasheet - Page 13

• Manufacturer Part Number: ISL23348UFVZ
• Description: IC DGTL POT 4CH 50K 20TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL23348UFVZ

• Taps: 128
• Resistance (ohms): 50K
• Number Of Circuits: 4
• Temperature Coefficient: 65 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C (Device Address)
• Voltage - Supply: 1.2 V ~ 5.5 V, 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Typical Performance Curves
Functional Pin Descriptions
Potentiometers Pins
RH
The high (RHi, i = 0, 1, 2, 3) and low (RLi, i = 0, 1, 2, 3) terminals
of the ISL23348 are equivalent to the fixed terminals of a
mechanical potentiometer. RHi and RLi are referenced to the
relative position of the wiper and not the voltage potential on the
terminals. With WRi set to 127 decimal, the wiper will be closest
to RHi, and with the WRi set to 0, the wiper is closest to RLi.
RW
RWi (i = 0, 1, 3) is the wiper terminal, and it is equivalent to the
movable terminal of a mechanical potentiometer. The position of
the wiper within the array is determined by the WRi register.
V
Power terminal for the potentiometer section analog power source.
Can be any value needed to support the voltage range of the DCP
pins, from 1.7V to 5.5V, independent of the V
CC
1V/DIV
0.2µs/DIV
I
0.5V/DIV, 0.2µs/DIV
-3dB FREQUENCY = 1.437MHz AT MIDDLE TAP
I
AND RL
FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME
FIGURE 23. 10kΩ -3dB CUT OFF FREQUENCY
CH1: RH TERMINAL
CH2: RW TERMINAL
I
13
SCL 9TH CLOCK OF THE
DATA BYTE (ACK)
LOGIC
WIPER
SCL
voltage.
(Continued)
ISL23348
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for I
interface. It receives device address, wiper address and data
from an I
clock SCL, and it shifts out data after each falling edge of the
serial clock.
SDA requires an external pull-up resistor, since it is an open drain
input/output.
SERIAL CLOCK (SCL)
This input is the serial clock of the I
requires an external pull-up resistor, since a master is an open
drain output.
DEVICE ADDRESS (A2, A1, A0)
The address inputs are used to set the least significant 3 bits of
the 7-bit I
address serial data stream must match with the Address input
FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE
0.5V/DIV
20µs/DIV
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
FIGURE 24. STANDBY CURRENT vs TEMPERATURE
-40
2
2
C external master device at the rising edge of the serial
C interface slave address. A match in the slave
-15
V
CC
10
= 5.5V, V
TEMPERATURE (°C)
LOGIC
35
2
V
C serial interface. SCL
CC
= 5.5V
= 1.7V, V
60
LOGIC
WIPER
85
V
CC
August 24, 2011
= 1.2V
110
FN7903.1
2
C