PIC18F1220-H/SO Microchip Technology, PIC18F1220-H/SO Datasheet - Page 82
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PIC18F1220-H/SO
Manufacturer Part Number
PIC18F1220-H/SO
Description
IC MCU 8BIT 4KB FLASH 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F1220-ISO.pdf
(308 pages)
Specifications of PIC18F1220-H/SO
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
18-SOIC (0.295", 7.50mm Width)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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PIC18F1220/1320
9.3
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are two Peripheral
Interrupt Enable registers (PIE1, PIE2). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 9-6:
DS39605F-page 80
PIE Registers
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
bit 7
Unimplemented: Read as ‘0’
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
RCIE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
Unimplemented: Read as ‘0’
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
-n = Value at POR
U-0
—
R/W-0
ADIE
R/W-0
RCIE
W = Writable bit
‘1’ = Bit is set
R/W-0
TXIE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
CCP1IE
R/W-0
© 2007 Microchip Technology Inc.
x = Bit is unknown
TMR2IE
R/W-0
TMR1IE
R/W-0
bit 0
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