PIC18F4585-H/PT Microchip Technology, PIC18F4585-H/PT Datasheet - Page 170

• Manufacturer Part Number: PIC18F4585-H/PT
• Description: IC MCU 8BIT 48KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4585-H/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 44-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2585/2680/4585/4680
TABLE 15-3:
DS39625C-page 168
INTCON
RCON
IPR1
PIR1
PIE1
IPR2
PIR2
PIE2
TRISB
TRISC
TMR1L
TMR1H
T1CON
TMR3H
TMR3L
T3CON
CCPR1L
CCPR1H
CCP1CON
ECCPR1L
ECCPR1H
ECCP1CON
Legend:
Note 1:
Name
2:
3:
(1)
(1)
— = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Compare, Timer1 or Timer3.
These bits or registers are available on PIC18F4X8X devices only.
These bits are available on PIC18F4X8X devices and reserved on PIC18F2X8X devices.
The SBOREN bit is only available when CONFIG2L<1:0> =
(1)
PORTB Data Direction Register
PORTC Data Direction Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Timer3 Register High Byte
Timer3 Register Low Byte
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
Enhanced Capture/Compare/PWM Register 1 (LSB)
Enhanced Capture/Compare/PWM Register 1 (MSB)
EPWM1M1 EPWM1M0
GIE/GIEH
OSCFIP
OSCFIF
OSCFIE
PSPIP
PSPIF
PSPIE
RD16
RD16
IPEN
Bit 7
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
—
SBOREN
T3ECCP1
PEIE/GIEL
CMIP
CMIE
CMIF
T1RUN
ADIP
ADIE
ADIF
Bit 6
—
(2)
(2)
(2)
(3)
(1)
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
T3CKPS1 T3CKPS0 T3CCP1
EDC1B1
TMR0IE
DC1B1
RCIP
RCIE
RCIF
Bit 5
—
—
—
—
Preliminary
EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0
INT0IE
DC1B0
EEIP
EEIE
Bit 4
TXIP
TXIF
TXIE
EEIF
RI
CCP1M3
SSPIP
SSPIF
SSPIE
BCLIP
BCLIE
BCLIF
RBIE
Bit 3
TO
01
; otherwise, it is disabled and reads as ‘
CCP1M2
T3SYNC
TMR0IF
CCP1IP
CCP1IE
CCP1IF
HLVDIP
HLVDIF
HLVDIE
Bit 2
PD
TMR1CS
TMR3CS
CCP1M1
TMR2IP
TMR2IE
TMR3IP
TMR3IE
TMR2IF
TMR3IF
INT0IF
Bit 1
POR
© 2007 Microchip Technology Inc.
ECCP1IP
ECCP1IF
ECCP1IE
TMR1ON
TMR3ON
CCP1M0
TMR1IP
TMR1IF
TMR1IE
RBIF
Bit 0
BOR
(2)
(2)
(2)
0
on page
Values
Reset
’.
49
50
52
52
52
51
52
51
52
52
50
50
50
51
51
51
51
51
51
51
51
51