NCP1910GEVB ON Semiconductor, NCP1910GEVB Datasheet - Page 19

• Manufacturer Part Number: NCP1910GEVB
• Description: BOARD EVAL NCP1910DEMO-B-TLS
• Manufacturer: ON Semiconductor
• Series: -r

Specifications of NCP1910GEVB

• Design Resources: NCP1910 Schematic NCP1910GEVB BOM
• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Power - Output: -
• Voltage - Output: Adj down to 0.8V
• Current - Output: 3A
• Voltage - Input: 3 ~ 5.5 V
• Regulator Topology: Buck
• Frequency - Switching: 1MHz
• Board Type: Fully Populated
• Utilized Ic / Part: NCP1910
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP1910GEVBOS

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Combo Management
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On board dead time: to eliminate the shoot−through
on the half−bridge leg, a dead time is included in the
controller (see DT
Soft−start: a dedicated pin discharges a capacitor to
ground upon start−up to offer a smooth output voltage
ramp up. The start−up frequency is the maximum set by
the resistor connected between R
capacitor connected from R
start duration. In fault mode, when the voltage on
CS/FF pin exceeds a typical value of 1 V, the soft−start
pin is immediately discharged and a re−start at high
frequency occurs.
Skip cycle operation: to avoid any frequency runaway
in light conditions but also to improve the standby
power consumption, the NCP1910B welcomes a skip
input (Skip pin) which permanently observes the
opto−coupler collector. If this pin senses a low voltage,
it cuts the LLC output pulses until the collector goes up
again. The NCP1910A does not offer the skip
capability and routes the analog ground on pin 16
instead.
High−voltage drivers: capitalizing on
ON Semiconductor technology, the LLC controller
includes a high−voltage section allowing a direct
connection to the high−voltage rail. The MOSFET leg
can therefore be directly driven without using a
gate−drive transformer.
Fault protection: as explained in the above lines, the
CS/FF pin combines a two−level protection circuit. If
the level crosses the first level (1 V), the LLC converter
immediately increases its switching frequency to the
maximum set by the external resistive divider
connected on R
protection mode. In case the fault is more severe, the
signal on the CS/FF pin crosses the second threshold
(1.5 V) and latches off the whole combo controller.
Reset occurs via an UVLO detection on V
the on/off pin or a brown−out detection on the PFC
stage. This latter confirms that the user has unplugged
and re−plugged the power supply.
Start−up delay: the PFC start−up sequence often
generates an output overshoot followed by damped
oscillations. To make sure the PFC output voltage is
fully stabilized before starting the LLC converter, a
20 ms delay is inserted after the internal PFC_ok signal
t
pin. This is an auto−recovery
L
parameter).
t
pin to ground fixes the soft
t
pin and SS pin. The
CC
, a reset on
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Principle of NCP1910 Scheme
PFC Section
input voltage is a rectified 50 Hz or 60 Hz sinusoidal signal.
The MOSFET is switching at a high frequency (typically
65 kHz in NCP1910) so that the inductor current I
consists of high and low−frequency components.
capacitor in order to eliminate the high−frequency
component of the inductor I
too bulky because it can pollute the power factor by
distorting the rectified sinusoidal input voltage.
A CCM PFC boost converter is shown in Figure 41. The
Filter capacitor C
is asserted. This delay is always reset when the combo
is started from a Vcc ULVO, line brown−out condition
or via the on/off pin.
Power good signal: the power good signal (PG) is
intended to instruct the downstream circuitry installed
on the isolated secondary side that the combo is
working. Once the PFC has started, an internal
“PFC_OK” signal is asserted. 20 ms later, the PG pin is
brought low. This signal can now disappear in two
cases: the bulk voltage decreases to an abnormal level,
programmed by a reference voltage imposed on PG
pin. This level is usually above the LLC turn−off
voltage, programmed by BO
normal turn−off sequence, PG first drops and signals
the secondary side that it must be prepared for
shutdown. The second event that can drop the PG
signal is when the PFC experiences a fault: broken
feedback path, severe overload. In this case, the PG
signal is immediately asserted high and a 5 ms timer
starts. Once this timer is elapsed, the LLC converter can
be safely halted.
Latched event: in the event of a severe operating
condition, the PFC can be latched (OVP2 pin) and/or
the LLC controller also (CS/FF pin). In either case, the
whole combo controller is locked and can only be reset
via a V
on pin on/off.
Thermal Shutdown: an internal thermal circuitry
disables the circuit gate drive and then keeps the power
switch off when the junction temperature exceeds
140°C typically. The circuit resumes operation once the
temperature drops below about 110°C (30°C
hysteresis).
CC
UVLO, line brown−out or a level transition
in
is an essential and very small value
L
. This filter capacitor cannot be
adj
pin. Therefore, in a
L
basically
adj