NCP1910GEVB ON Semiconductor, NCP1910GEVB Datasheet - Page 27

• Manufacturer Part Number: NCP1910GEVB
• Description: BOARD EVAL NCP1910DEMO-B-TLS
• Manufacturer: ON Semiconductor
• Series: -r

Specifications of NCP1910GEVB

• Design Resources: NCP1910 Schematic NCP1910GEVB BOM
• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Power - Output: -
• Voltage - Output: Adj down to 0.8V
• Current - Output: 3A
• Voltage - Input: 3 ~ 5.5 V
• Regulator Topology: Buck
• Frequency - Switching: 1MHz
• Board Type: Fully Populated
• Utilized Ic / Part: NCP1910
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP1910GEVBOS

PFC Power Boost
feed-forward, the power delivery is independent from input
voltage. It brings benefit of good power factor and a direct
control on the frequency foldback. However, in some special
case such as when the ac input voltage drops sharply from
high line to low line, the power will be limited because the
filter on LBO pin slows down the reaction speed to follow
up the change on input voltage. In the end, the bulk voltage
might drop too low and stop the LLC converter.
function inside. The idea is to pull down LBO pin to 2 V
typically, V
•
•
•
t
t
•
LBO(PDlimit)
LBO(PDblank)
As depicted in previous section, thanks to the V
Hence, NCP1910 builds a so-called PFC power boost
The maximum pulling-down duration is defined by
V
line, and
V
t
V
triggered.
Over−Voltage Protection (OVP): When V
than 105% of V
bulk voltage), the PFC driver output goes low for
protection. The circuit automatically resumes operation
when V
around 44 mV hysteresis in the OVP comparator. If the
nominal V
PFCflag
LBO
CTRL
bulk
is under 95% of nominal output, i.e. VLD is
is above 2 V, V
, and,
is at maximum for more than timer defined by
FB
LBO(PD)
, which is 5 ms typically. A blanking timer,
, is to avoid this power boost function reacting
bulk
becomes lower than 103.2% of V
is set at 390 V, then the maximum bulk
PREF
C
, when
FB
R
FBU
(i.e. V
LBO(PD)
FB
R
bulk
V
FBL
CTRL
, i.e. the input is at high
> 105% of nominal
105% V
95% V
V
PREF
PREF
PREF
Figure 52. PFC OVP and VLD
FB
PREF
is higher
+
−
, i.e.
http://onsemi.com
OTA
in
2
PFC_OVP
V
bulk
VLD
$30 mA
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too soon, which is about 77 ms typically. The PFC power
boost function is inhibited at start-up until bulk voltage is
above 95% of nominal output.
PFC Skip Mode
conditions, the circuit skips cycles when V
minimum level. V
and 3.6 V due to the internal active clamps. A skip sequence
occurs as long as the 0.6 V clamp circuitry is triggered and
switching operations is recovered when the clamp is
inactive.
Fast Transient Response
output voltage of PFC stages may exhibit excessive over or
under−shoots because of abrupt load or input voltage
variations (such as start−up duration). As shown in
Figure 52, if the output voltage is out of regulation,
NCP1910 has 2 functions to maintain the output voltage
regulation.
•
PFC_OK
In order to ensure a proper regulation in no load
Given the low bandwidth of the regulation block, the
voltage is 105% of 390 V = 410 V. Hence a cost and
size effective bulk capacitor of lower voltage rating is
suitable for this application,
Voltage−Low Detection (VLD): NCP1910 drastically
speeds up the regulation loop by its internal 200 mA
enhanced current source when the bulk voltage is below
95% of its regulation level. Under normal condition, the
PFC_OPL
CTRL
Vdd
is maintained between about 0.6 V
200 mA
I
VLD
CTRL
is at its