NCP1910GEVB ON Semiconductor, NCP1910GEVB Datasheet - Page 34

• Manufacturer Part Number: NCP1910GEVB
• Description: BOARD EVAL NCP1910DEMO-B-TLS
• Manufacturer: ON Semiconductor
• Series: -r

Specifications of NCP1910GEVB

• Design Resources: NCP1910 Schematic NCP1910GEVB BOM
• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Power - Output: -
• Voltage - Output: Adj down to 0.8V
• Current - Output: 3A
• Voltage - Input: 3 ~ 5.5 V
• Regulator Topology: Buck
• Frequency - Switching: 1MHz
• Board Type: Fully Populated
• Utilized Ic / Part: NCP1910
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP1910GEVBOS

LLC High−Voltage Driver
direct connection to the upper side MOSFET of LLC
converter. This device also incorporates an upper UVLO
circuitry that makes sure enough gate voltage is available for
the upper side MOSFET. The bias of the floating driver
section is provided by C
HB pin that is refilled by external booststrap diode. The
floating portion can go up to 600 Vdc and makes the IC
perfectly suitable for offline applications featuring a 400 V
PFC front−end stage.
Combo Management Section
Start−up and Stop Delay of LLC and Pgout signal
(t
if the PFC is not ready.
PFCok signal is asserted high when V
normal bulk voltage. After PFCok signal is high, a timer
(t
starts. When t
LLC starts its driver outputs (ML and MU pins).
out situation, PG
Remote on/off (on/off pin)
feature at on/off pin:
•
DEL1
DEL1
LLC works
The NCP1910 includes a high−voltage driver allowing a
To ensure the proper operation of LLC, LLC cannot start
As depicted in the “PFCok signal” section, the internal
In case of shutdown by unplugging ac input or line brown
NCP1910 reserves one dedicated pin for remote control
When the on/off pin is pulled below 1 V, the PFC starts
operation. 20 ms after V
level, LLC starts.
PG
95%
) starts to ensure PFC stage is fully stable before LLC
and t
out
DEL2
DEL1
V
)
bulk
out
is elapsed, PG
signal is released open. And then
boot
off
bulk
capacitor between V
is above 95% of target
out
bulk
pin is grounded and
Figure 61. The Timing for t
is above 95% of
20 ms
t
DEL1
boot
pin and
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34
another timer (t
stops its drivers (ML and MU pins).
PG
Once the PFC is ready (PFCok is asserted high), t
(20 ms typically) is started. Once this delay is elapsed:
•
•
As shutdown by unplug ac input, V
•
•
As shutdown by line brown−out situation, PFCok signal will
be pulled down:
•
•
•
Figure 61 depicts the start−up and stop delay of LLC and
PG
LLC drivers (ML and MU pins) can start to operate.
When it reaches the PG signal, which is adjusted by
PG
If V
by BO
e.g. light load, LLC drivers (ML and MU pins) will
stop 5 ms after PG
PG
signal is low.
LLC drivers (ML and MU pins) will stop 5 ms after
PG
When the on/off pin is above 3 V, the device stops both
PFC and LLC immediately and keeps low
consumption. Figure 62 depicts the relationship
between the operation mode and on/off pin.
out
DEL1
.
out
adj
out
out
bulk
and t
pin, PG
pin is asserted low
pin is released open once this internal PFCok
pin is released open (t
adj
reaches the LLC stop level (BO level adjusted
pin), the LLC stops; or if V
DEL2
DEL2
out
pin is released open.
) starts. Once the t
out
pin is released (t
DEL2
off
PG level
BO level
bulk
).
t
5 ms
DEL2
DEL2
decreases:
bulk
DEL2
is elapsed, LLC
drops slowly,
).
time
DEL1