AGLN250V2-ZCSG81 Actel, AGLN250V2-ZCSG81 Datasheet - Page 89

• Manufacturer Part Number: AGLN250V2-ZCSG81
• Manufacturer: Actel

Table 2-96 • RAM4K9
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
AS
AH
ENS
ENH
BKS
BKH
DS
DH
CKQ1
CKQ2
C2CWWL
C2CRWH
C2CWRH
RSTBQ
REMRSTB
RECRSTB
MPWRSTB
CYC
MAX
For specific junction temperature and voltage supply levels, refer to
values.
1.2 V DC Core Voltage
Address setup time
Address hold time
REN_B, WEN_B setup time
REN_B, WEN_B hold time
BLK_B setup time
BLK_B hold time
Input data (DI) setup time
Input data (DI) hold time
Clock HIGH to new data valid on DO (output retained, WMODE = 0)
Clock HIGH to new data valid on DO (flow-through, WMODE = 1)
Clock HIGH to new data valid on DO (pipelined)
Address collision clk-to-clk delay for reliable write after write on same address;
applicable to closing edge
Address collision clk-to-clk delay for reliable read access after write on same
address; applicable to opening edge
Address collision clk-to-clk delay for reliable write access after read on same
address; applicable to opening edge
RESET_B LOW to data out LOW on DO (flow-through)
RESET_B LOW to data out LOW on DO (pipelined)
RESET_B removal
RESET_B recovery
RESET_B minimum pulse width
Clock cycle time
Maximum frequency
Commercial-Case Conditions: T
J
= 70°C, Worst-Case V
Description
A dv a n c e v 0. 3
CC
= 1.14 V
IGLOO nano DC and Switching Characteristics
Table 2-7 on page 2-7
10.90
Std.
1.53
0.29
1.50
0.29
3.05
0.29
1.33
0.66
6.61
5.72
3.38
0.30
0.89
1.01
3.86
3.86
1.12
5.93
1.18
for derating
92
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2 - 75