USB3500-ABZJ Standard Microsystems (SMSC), USB3500-ABZJ Datasheet - Page 27

• Manufacturer Part Number: USB3500-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of USB3500-ABZJ

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: QFN
• Rad Hardened: No
• Lead Free Status / Rohs Status: Compliant

Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface
Datasheet
SMSC USB3500
6.4.3
6.5
6.6
6.6.1
SIGNALING MODE
OTG device, Peripheral HS/FS Resume
OTG device, Peripheral Test J/Test K
Crystal Oscillator and PLL
Internal Regulators and POR
Bias Generator
This block consists of an internal bandgap reference circuit used for generating the high speed driver
currents and the biasing of the analog circuits. This block requires an external 12KΩ, 1% tolerance,
external reference resistor connected from RBIAS to ground.
The USB3500 uses an internal crystal driver and PLL sub-system to provide a clean 480MHz reference
clock that is used by the PHY during both transmit and receive. The USB3500 requires a clean 24MHz
crystal or clock as a frequency reference. If the 24MHz reference is noisy or off frequency the PHY
may not operate correctly.
The USB3500 can use either a crystal or an external clock oscillator for the 24MHz reference. The
crystal is connected to the XI and XO pins as shown in the application diagram,
oscillator is used, the clock should be connected to the XI input and the XO pin left floating. When
using an external clock, the clock source must be clean so it does not degrade performance, and
should be be driven with a 0 to 3.3 volt signal.
After the 480MHz PLL has locked to the correct frequency, it will drive the CLKOUT pin with a 60MHz
clock. The USB3500 is guaranteed to start the clock within the time specified in
The USB3500 includes integrated power management functions to reduce the bill of materials and
simplify product design.
Internal Regulators
The USB3500 has two internal regulators that create two 1.8V outputs (labeled VDD1.8 and VDDA1.8)
from the 3.3 volt power supply input (VDD3.3). Each regulator requires an external 4.7uF +/-20% low
ESR bypass capacitor to ensure stability. X5R or X7R ceramic capacitors are recommended since they
exhibit an ESR lower that 0.1ohm at frequencies greater than 10kHz.
The specific capacitor recommendations for each pin are detailed in
Locations", and shown in Figure 7.10, "USB3500 Application Diagram (Top View)".
Note: The USB3500 regulators are designed to generate a 1.8volt supply for the USB3500 only.
Using the regulators to provide current for other circuits is not recommended and SMSC does
not guarantee USB performance or regulator stability in this case.
Table 6.1 DP/DM termination vs. Signaling Mode (continued)
UTMI+ INTERFACE SETTINGS
01b
00b
DATASHEET
1b
0b
27
10b
10b
0b
0b
1b
1b
1b
0b
RESISTOR SETTINGS
Table 3.1, "USB3500 Pin
0b
0b
Figure
Table
Revision 1.0 (06-05-08)
0b
0b
5.2.
7.10. If a clock
1b
1b
0b
1b