C8051T605-GSR Silicon Laboratories Inc, C8051T605-GSR Datasheet - Page 106

• Manufacturer Part Number: C8051T605-GSR
• Description: MCU 8-Bit C8051T60x 8051 CISC 2KB EPROM 1.8V/3V 14-Pin SOIC T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051T605-GSR

• Package: 14SOIC
• Device Core: 8051
• Family Name: C8051T60x
• Maximum Speed: 25 MHz
• Ram Size: 256 Byte
• Program Memory Size: 2 KB
• Operating Supply Voltage: 1.8|3 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 8
• Interface Type: I2C/SMBus/UART
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

C8051T600/1/2/3/4/5/6
22. Port Input/Output
Digital and analog resources are available through eight I/O pins on the C8051T600/1/2/3/4/5, or six I/O
pins on the C8051T606. Port pins P0.0-P0.7 can be defined as general-purpose I/O (GPIO), assigned to
one of the internal digital resources, or assigned to an analog function as shown in Figure 22.1. Port pin
P0.7 is shared with the C2 Interface Data signal (C2D). The designer has complete control over which
functions are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility
is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always
be read in the P0 port latch, regardless of the crossbar settings.
The crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 22.3 and Figure 22.4). The registers XBR1 and XBR2, defined in SFR Definition 22.2 and SFR
Definition 22.3, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 22.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (P0MDOUT). Complete Electrical
Specifications for Port I/O are given in Section “8. Electrical Characteristics” on page 30.
106
Highest
Priority
Lowest
Priority
SYSCLK
Outputs
SMBus
T0, T1
UART
PCA
CP0
Figure 22.1. Port I/O Functional Block Diagram
Port Latch
2
2
2
4
2
P0
(P0.0-P0.7)
8
Rev. 1.2
XBR2 Registers
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
(ADC0, CP0, VREF, EXTCLK)
To Analog Peripherals
8
P0MDIN Registers
P0MDOUT,
Cells
I/O
P0
P0.0
(‘T600/1/2/3/4/5 Only)
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
(‘T600/1/2/3/4/5 Only)
P0.7