C8051T605-GSR Silicon Laboratories Inc, C8051T605-GSR Datasheet - Page 170

• Manufacturer Part Number: C8051T605-GSR
• Description: MCU 8-Bit C8051T60x 8051 CISC 2KB EPROM 1.8V/3V 14-Pin SOIC T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051T605-GSR

• Package: 14SOIC
• Device Core: 8051
• Family Name: C8051T60x
• Maximum Speed: 25 MHz
• Ram Size: 256 Byte
• Program Memory Size: 2 KB
• Operating Supply Voltage: 1.8|3 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 8
• Interface Type: I2C/SMBus/UART
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

C8051T600/1/2/3/4/5/6
26.4. Watchdog Timer Mode
A programmable Watchdog Timer (WDT) function is available through the PCA Module 2. The WDT is
used to generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a
specified limit. The WDT can be configured and enabled/disabled as needed by software.
With the WDTE bit set in the PCA0MD register, Module 2 operates as a Watchdog Timer (WDT). The Mod-
ule 2 high byte is compared to the PCA counter high byte; the Module 2 low byte holds the offset to be
used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some
PCA registers are restricted while the Watchdog Timer is enabled. The WDT will generate a reset
shortly after code begins execution. To avoid this reset, the WDT should be explicitly disabled (and option-
ally re-configured and re-enabled if it is used in the system).
26.4.1. Watchdog Timer Operation
While the WDT is enabled:






While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but
user software has not enabled the PCA counter. If a match occurs between PCA0CPH2 and PCA0H while
the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a
write of any value to PCA0CPH2. Upon a PCA0CPH2 write, PCA0H plus the offset held in PCA0CPL2 is
loaded into PCA0CPH2 (See Figure 26.10).
170
PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS2–CPS0) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 2 is forced into software timer mode.
Writes to the Module 2 mode register (PCA0CPM2) are disabled.
PCA0CPL2
C
D
L
I
W
D
T
E
PCA0MD
W
D
C
K
L
Figure 26.10. PCA Module 2 with Watchdog Timer Enabled
PCA0CPH2
C
P
S
2
Write to
C
P
S
1
C
P
S
0
C
E
F
8-bit Adder
Enable
Adder
Enable
Rev. 1.2
PCA0CPH2
Comparator
PCA0H
8-bit
Match
PCA0L Overflow
Reset