KMPC8548ECVTAUJC Freescale Semiconductor, KMPC8548ECVTAUJC Datasheet - Page 14

• Manufacturer Part Number: KMPC8548ECVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548ECVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Power Characteristics
3
The estimated typical power dissipation for the core complex bus (CCB) versus the core frequency for this
family of PowerQUICC III devices is shown in
4
This section discusses the timing for the input clocks.
4.1
Table 5
14
At recommended operating conditions (see
Notes:
1. CCB frequency is the SoC platform frequency, which corresponds to the DDR data rate.
2. SLEEP is based on V
3. Typical-65 is based on V
4. Typical-105 is based on V
5. Maximum is based on V
SYSCLK frequency
SYSCLK cycle time
SYSCLK rise and fall time
SYSCLK duty cycle
CCB Frequency
Power Characteristics
Input Clocks
provides the system clock (SYSCLK) AC timing specifications for the MPC8548E.
400
500
533
System Clock Timing
Parameter/Condition
From a system standpoint, if any of the I/O power supplies ramp prior to the
V
one or zero during power-up, and extra current may be drawn by the device.
1
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
DD
core supply, the I/Os associated with that I/O supply may drive a logic
DD
Core Frequency
DD
DD
= 1.1 V, T
DD
= 1.1 V, T
= 1.1 V, T
= 1.1 V, T
1000
1200
1500
1333
800
j
Table 5. SYSCLK AC Timing Specifications
= 65°C.
j
j
Table 4. MPC8548E Power Dissipation
= 105°C, running a smoke test.
= 65°C, running Dhrystone.
j
= 105°C, running Dhrystone.
Table
2) with OV
SLEEP
t
11.5
KHK
2.7
2.7
2.7
6.2
Symbol
f
t
t
SYSCLK
SYSCLK
KH
/t
SYSCLK
, t
Table
2
NOTE
KL
DD
= 3.3 V ± 165 mV
4.
Typical-65
13.6
4.6
5.0
5.4
7.9
Min
7.5
0.6
16
40
3
.
Typical-105
Typ
1.0
—
—
—
16.5
10.8
7.5
7.9
8.3
4
Max
133
1.2
60
60
Maximum
Freescale Semiconductor
18.6
12.8
8.1
8.5
8.9
MHz
Unit
ns
ns
%
5
1, 6, 7, 8
Notes
6, 7, 8
Unit
W
W
W
W
2
3