KMPC8548ECVTAUJC Freescale Semiconductor, KMPC8548ECVTAUJC Datasheet - Page 76

• Manufacturer Part Number: KMPC8548ECVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548ECVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PCI Express
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the
TX UI.
16.5.1
The AC timing and voltage parameters must be verified at the measurement point, as specified within
0.2 inches of the package pins, into a test/measurement load shown in
76
Compliance Test and Measurement Load
Figure 49. Minimum Receiver Eye Timing and Voltage Compliance Specification
The reference impedance for return loss measurements is 50. to ground for
both the D+ and D– line (that is, as measured by a vector network analyzer
with 50-Ω probes—see
optional for the return loss measurement.
The allowance of the measurement point to be within 0.2 inches of the
package pins is meant to acknowledge that package/board routing may
benefit from D+ and D– not being exactly matched in length at the package
pin boundary.
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
(D+ D– Crossing Point)
V
RX-DIFF
D+ Package
D+ Package
D– Package
= 0 mV
Figure 50. Compliance Test/Measurement Load
+ Package
Silicon
Pin
Pin
Pin
TX
Figure
V
RX-DIFFp-p-MIN
0.4 UI = T
50). Note that the series capacitors, CTX, are
C = C
C = C
NOTE
NOTE
R = 50 Ω
RX-EYE-MIN
TX
TX
> 175 mV
(D+ D– Crossing Point)
R = 50 Ω
V
Figure
RX-DIFF
50.
= 0 mV
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