DS21352L+ Maxim Integrated Products, DS21352L+ Datasheet - Page 50

• Manufacturer Part Number: DS21352L+
• Description: IC TXRX T1 1-CHIP 3.3V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21352L+

• Function: Single-Chip Transceiver
• Interface: HDLC, T1
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: DSX-1 and CSU Line Build-Out Generator, HDLC Controller, In-Band Loop Code Generator and Detector
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

IMR2: INTERRUPT MASK REGISTER 2 (Address=6F Hex)
8. ERROR COUNT REGISTERS
There are a set of three counters that record bipolar violations, excessive zeros, errors in the CRC6 code
words, framing bit errors, and number of multiframes that the device is out of receive synchronization.
Each of these three counters are automatically updated on either one second boundaries (CCR3.2=0) or
every 42 ms (CCR3.2=1) as determined by the timer in Status Register 2 (SR2.5). Hence, these registers
contain performance data from either the previous second or the previous 42 ms. The user can use the
interrupt from the one second timer to determine when to read these registers. The user has a full second
(or 42 ms) to read the counters before the data is lost. All three counters will saturate at their respective
maximum counts and they will not rollover (note: only the Line Code Violation Count Register has the
potential to over-flow but the bit error would have to exceed 10E-2 before this would occur).
SYMBOL
(MSB)
RMTCH
RMF
RFDL
TFDL
RMF
TMF
RAF
SEC
RSC
POSITION
TMF
IMR2.7
IMR2.6
IMR2.5
IMR2.4
IMR2.3
IMR2.2
IMR2.1
IMR2.0
NAME AND DESCRIPTION
Receive Multiframe.
0 = interrupt masked
1 = interrupt enabled
Transmit Multiframe.
0 = interrupt masked
1 = interrupt enabled
One Second Timer.
0 = interrupt masked
1 = interrupt enabled
Receive FDL Buffer Full.
0 = interrupt masked
1 = interrupt enabled
Transmit FDL Buffer Empty.
0 = interrupt masked
1 = interrupt enabled
Receive FDL Match Occurrence.
0 = interrupt masked
1 = interrupt enabled
Receive FDL Abort.
0 = interrupt masked
1 = interrupt enabled
Receive Signaling Change.
0 = interrupt masked
1 = interrupt enabled
SEC
RFDL
50 of 137
TFDL
RMTCH
RAF
(LSB)
RSC