SI3200-G-FSR Silicon Laboratories Inc, SI3200-G-FSR Datasheet - Page 17

• Manufacturer Part Number: SI3200-G-FSR
• Description: IC SLIC/CODEC 100V LINE 16SOIC
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3200-G-FSR

• Function: Subscriber Line Interface Concept (SLIC), CODEC
• Interface: GCI, PCM, SPI
• Number Of Circuits: 2
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 110µA
• Power (watts): 941mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Includes: Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 12. Switching Characteristics—SPI
(V
Parameter
Cycle Time SCLK
Rise Time, SCLK
Fall Time, SCLK
Delay Time, SCLK Fall to SDO Active
Delay Time, SCLK Fall to SDO
Transition
Delay Time, CS Rise to SDO Tri-state
Setup Time, CS to SCLK Fall
Hold Time, CS to SCLK Rise
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time between Chip Selects
SDI to SDITHRU Propagation Delay
Notes:
DD
1. All timing is referenced to the 50% level of the waveform. Input test levels are V
2. The minimum SCLK cycle time is based on a single Si3220 connected to the SPI bus. If multiple Si3220s are
, V
DD1
connected to the same SPI bus, please contact a Silicon Laboratories representative for the recommended minimum
SCLK cycle time for your application.
– V
1
DD4
SDITHRU
= 3.13 to 5.25 V, T
2
SCLK
SDO
SDI
CS
A
t
= 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade, C
su1
t
d1
Figure 1. SPI Timing Diagram
Symbol
t
r
t
t
t
t
t
t
t
t
t
su1
su2
t
d1
d2
d3
h1
h2
d4
t
t
cs
c
r
f
Rev. 1.3
Test Conditions
t
su2
t
c
t
d2
t
h2
t
d4
Si3220/25 Si3200/02
IH
Min
220
62
—
—
—
—
—
25
20
25
20
—
= V
t
f
t
DDD
h1
–0.4 V, V
L
= 20 pF)
Typ
—
—
—
—
—
—
—
—
—
—
—
4
t
cs
t
d3
IL
= 0.4 V
Max
25
25
20
20
20
10
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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