SI3200-G-GS Silicon Laboratories Inc, SI3200-G-GS Datasheet
SI3200-G-GS
Specifications of SI3200-G-GS
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SI3200-G-GS Summary of contents
Page 1
... PCM/SPI or GCI bus digital interfaces. The Si3200/2 linefeed ICs perform all high-voltage functions and operate from a 3 supply as well as single or dual battery supplies up to 100 V (Si3200) or 125 V (Si3202). The Si3220 and Si3225 are available in a 64-pin thin quad flat package (TQFP), and the Si3200/2 is available in a thermally-enhanced 16-pin small outline (SOIC) package ...
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... Si3220/25 Si3200/02 2 Rev. 1.3 ...
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... PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.30. PCM Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.31. General Circuit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.32. System Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4. Pin Descriptions: Si3220/ 101 5. Pin Descriptions: Si3200 105 6. Package Outline: 64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 7. Package Outline: 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8. Silicon Labs Si3220/25 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9. Dual ProSLIC Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Document Change List ...
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... On Si3200 revision E, the dv/dt of the voltage applied to the V 4. Operation of the Si3220/Si3225 above 125 °C junction temperature may degrade device reliability. The Si3200/Si3202 should be operated at a junction temperature below 140 °C for optimal reliability. ...
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... On Si3200 revision E, the dv/dt of the voltage applied to the V 4. Operation of the Si3220/Si3225 above 125 °C junction temperature may degrade device reliability. The Si3200/Si3202 should be operated at a junction temperature below 140 °C for optimal reliability. ...
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... Supply Voltage, Si3220/Si3225 Supply Voltage, Si3200/Si3202 High Battery Supply Voltage, Si3200 Low Battery Supply Voltage, Si3200 High Battery Supply Voltage, Si3202 Low Battery Supply Voltage, Si3202 *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. ...
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... See "3.14.4. Ringing Power Considerations" on page 54 for current and power consumption under other operating conditions. 3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must include an additional ( BAT Si3220/25 Si3200/02 1 (Continued) Test Condition Sleep mode, RESET = 0 Open (high-impedance) Active on-hook standby ...
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... Si3220/25 Si3200/02 Table 3. 3.3 V Power Supply Characteristics = = ( – °C for K/F-Grade, – °C for B/G-Grade) DD DD1 DD4 A Parameter Symbol Chipset Power P SLEEP Consumption P OPEN P STBY 3 P ACTIVE P OHT P RING Notes: 1. All specifications are for a single channel based on measurements with both channels in the same operating state. ...
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... See "3.14.4. Ringing Power Considerations" on page 54 for current and power consumption under other operating conditions. 3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must include an additional ( BAT Si3220/25 Si3200/02 1 Test Condition Sleep mode, RESET = 0 VDD4 Open (high-impedance) Active on-hook standby ...
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... Si3220/25 Si3200/02 Table Power Supply Characteristics = = ( – °C for K/F-Grade, – °C for B/G-Grade) DD DD1 DD4 A Parameter Symbol V Supply Current I BAT VBAT (Si3200/2) Chipset Power P SLEEP Consumption P OPEN P STBY P ACTIVE P OHT P RING Notes: 1. All specifications are for a single channel based on measurements with both channels in the same operating state. ...
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... This per-pin total current setting should be selected so it can accommodate the sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given application. Si3220/25 Si3200/ °C for K/F-Grade, – °C for B/G-Grade) Test Condition TX/RX Performance 2-Wire – ...
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... Si3220/25 Si3200/02 Table 5. AC Characteristics (Continued – V 3. DD1 DD4 A Parameter 6 Idle Channel Noise PSRR from V – V DD1 DD4 PSRR from V BAT Longitudinal to Metallic/PCM Balance (forward or reverse) Metallic/PCM to Longitudinal Balance 7 Longitudinal Impedance 7 Longitudinal Current per Pin Notes: 1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should be – ...
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... CPE; hence the specified total loop resistance is R DC,MAX 3. Ringing amplitude is set for 93 V peak using the RINGAMP RAM address and measured at TIP-RING using no series protection resistance. Si3220/25 Si3200/ °C for K/F-Grade, – °C for B/G-Grade) Symbol ...
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... Si3220/25 Si3200/02 Table 6. Linefeed Characteristics (Continued – V 3. DD1 DD4 A Parameter Loop Voltage Sense Accuracy Loop Current Sense Accuracy Power Alarm Threshold Accuracy Notes: 1. Adaptive linefeed is enabled when the VOCDELTA RAM address is set to a non-zero value and is disabled when VOCDELTA is set to 0. ...
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... Table 8. Si3200/2 Characteristics = = (V 3. °C for K/F-Grade, – °C for B/G-Grade Parameter TIP/RING Pulldown Transistor Satura- tion Voltage TIP/RING Pullup Transistor Saturation Voltage Battery Switch Saturation Impedance OPEN State TIP/RING Leakage Current Internal Blocking Diode Forward Voltage Notes 600 Ω. ...
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... Si3220/25 Si3200/02 Table 10. DC Characteristics ( – V 3. DD1 DD4 A Parameter Symbol High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage SDITHRU internal pullup resistance Relay Driver Source Imped- R ance Relay Driver Sink Impedance Input Leakage Current Table 11. Switching Characteristics— ...
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... The minimum SCLK cycle time is based on a single Si3220 connected to the SPI bus. If multiple Si3220s are connected to the same SPI bus, please contact a Silicon Laboratories representative for the recommended minimum SCLK cycle time for your application. SCLK CS SDI SDO SDITHRU Si3220/25 Si3200/ °C for K/F-Grade, – °C for B/G-Grade, C Symbol Test Conditions ...
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... Si3220/25 Si3200/02 Table 13. Switching Characteristics—PCM Highway Interface = ( – V 3. DD1 DD4 A Parameter PCLK Period Valid PCLK Inputs 2 FSYNC Period PCLK Duty Cycle Tolerance PCLK Period Jitter Tolerance Rise Time, PCLK Fall Time, PCLK Delay Time, PCLK Rise to DTX Active ...
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... PCLK FSYNC DRX DTX Figure 2. PCM Highway Interface Timing Diagram Si3220/25 Si3200/ Rev. 1 ...
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... Si3220/25 Si3200/02 Table 14. Switching Characteristics—GCI Highway Serial Interface = ( – V 3. DD1 DD4 A 1 Parameter PCLK Period (2.048 MHz PCLK Mode) PCLK Period (4.096 MHz PCLK Mode) 2 FSYNC Period PCLK Duty Cycle Tolerance FSYNC Jitter Tolerance Rise Time, PCLK Fall Time, PCLK ...
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... PCLK t su1 FSYNC Frame 0, DRX Bit DTX Figure 4. GCI Highway Interface Timing Diagram (4.096 MHz PCLK Mode) Acceptable Region Figure 5. Transmit and Receive Path SNDR Si3220/25 Si3200/ su2 Frame 0, Bit 0 Rev. 1 ...
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... Si3220/25 Si3200/02 Fundamental Output Power (dBm0) Figure 6. Overload Compression Performance 5 0 −5 −10 −15 −20 −25 −30 −35 −40 −45 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 4500 4750 5000 0.4 ...
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... Figure 8. Receive Path Frequency Response Si3220/25 Si3200/02 RX Attenuation Distortion Frequency (Hz) RX Pass−Band Detail Frequency (Hz) Rev. 1.3 23 ...
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... Si3220/25 Si3200/02 1100 1000 900 800 700 600 500 400 300 200 100 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 Figure 9. Transmit Group Delay Distortion 1100 1000 900 800 700 600 ...
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... Si3220/25 Si3200/02 Rev. 1.3 25 ...
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... Si3220/25 Si3200/02 26 Rev. 1.3 ...
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... Si3220/25 Si3200/02 Rev. 1.3 27 ...
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... Si3220/25 Si3200/02 2. Bill of Materials Table 15. Si3220 + Si3200 External Component Values Component Value C1, C2, C11, C12 100 nF, 100 V, X7R, ±20% Filter capacitors for TIP, RING ac-sensing inputs. C3, C4, C13, C14 10 nF, 100 V, X7R, ±20% C5, C6, C15, C16 1 µF, 6.3 V, X7R, ±20% C30–C33 0.1 µ ...
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... Table 17. Si3225 + Si3200 External Component Values Component C1, C2, C11, C12 100 nF, 100 V, X7R, ±20% Filter capacitors for TIP, RING ac sensing inputs. C3, C4, C13, C14 10 nF, 100 V, X7R, ±20% C5, C6, C15, C16 1 µF, 6.3 V, X7R, ±20 C30 , C31 , C32, C33 0.1 µF, 100 V, Y5V C20– ...
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... The Si3220 and Si3225 are available in a 64-lead TQFP, and the Si3200/2 is available in a thermally-enhanced 16-lead SOIC. 3.1. Dual ProSLIC Architecture The Dual ProSLIC chipset is comprised of a low-voltage CMOS device that uses a low-cost integrated linefeed ...
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... Power Supply Sequencing Note: This section applies to Si3200 revision E only. To ensure proper operation, the following power sequencing guidelines should be followed: V should be allowed to reach its steady state DD voltage at least 20 ms before V BATH begin to ramp to its desired voltage. Transients and oscillations with a dv/dt above 10 V/ µ ...
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... TIP and RING. Sense resistor R DC RING; Capacitor C the TIP and RING leads to be measured. The Si3220 and Si3225 both use the Si3200/2 to drive TIP and with a RING and isolate the high-voltage line from the low- voltage CMOS devices. = –56 V and ...
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... The register and RAM locations Open (LF[2:0] = 000). The Si3200/2 output is high-impedance. This mode can be used in the presence of line fault conditions and to generate open-switch intervals (OSIs). The device can also automatically enter the open state if excess power consumption is detected in the Si3200 the discrete bipolar transistors. ...
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... Si3220/25 Si3200/02 Table 19. Register and RAM Locations for Linefeed Control Parameter Register/ Mnemonic Linefeed LINEFEED Linefeed Shadow LINEFEED Battery Feed Control RLYCON Loop Current Limit On-Hook Line Voltage Common Mode Voltage V Delta for Off-Hook VOCDELTA OC V Delta Threshold, Low VOCLTH OC V Delta Threshold, High ...
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... Figure 16. Adaptive Linefeed V/I Behavior When the Si3220/Si3225 is used with the Si3200/2 linefeed device, the source impedance of the dc feed is 640 Ω before the adaptive linefeed transition and 320 Ω after the adaptive linefeed transition, as shown in Figure 16. On the other hand, when the Si3220/Si3225 is used with a discrete bipolar transistor linefeed, the source impedance of the dc feed is 320 Ω ...
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... Si3220/25 Si3200/02 transition point. In the case of the discrete bipolar linefeed, since the source impedance is 320 Ω both before and after the adaptive linefeed transition, the V/I curve exhibits no discontinuity at the transition points when VOCDELTA = 0. 3.4.3. Off-Hook to On-Hook Transition Load lines Ω , 1930 Ω, and 1800 Ω are shown in Figure 16 ...
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... The Dual ProSLIC devices can prevent thermal overloads by regulating the total power inside the Si3200 each of the external bipolar transistors (if using a discrete linefeed circuit). The DSP engine performs all power calculations and provides the ...
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... Si3220/25 Si3200/02 Table 21. Register and RAM Locations Used for Loop Monitoring Parameter Register/RAM Mnemonic Loop Voltage Sense VLOOP (V – TIP RING TIP Voltage Sense VTIP RING Voltage Sense VRING Loop Current Sense ILOOP Battery Voltage Sense VBAT Longitudinal Current ILONG Sense ...
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... SOT–23 package) PLPF56 = Q5/Q6 thermal LPF pole = 0x000E (for SOT–223 package) In the case where the Si3200/2 is used, thermal filtering needs to be performed only on the total power reflected in the PSUM RAM location. When the filter output exceeds the total power threshold, an interrupt is issued ...
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... IRQVEC3 register are set when a power alarm is triggered in the respective transistor. When using the Si3200/2, the PQ1E bit enables the power alarm interrupt, and the PQ1S bit is set when a Si3200 power alarm is triggered. 3.8.5. Power Dissipation Considerations The Dual ProSLIC devices rely on the Si3200/2 to power the line from the battery supply ...
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... Si3200/2 Total Power Output Monitor Si3200/2 Power Alarm Interrupt Pending Si3200/2 Power Alarm Interrupt Enable Q1/Q2 Power Alarm Threshold (discrete) Q1/Q2 Power Alarm Threshold (Si3200/2) Q3/Q4 Power Alarm Threshold Q5/Q6 Power Alarm Threshold Q1/Q2 Thermal LPF Pole Q3/Q4 Thermal LPF Pole Q5/Q6 Thermal LPF Pole Q1– ...
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... Si3220/25 Si3200/02 3.9. Automatic Dual Battery Switching The Dual ProSLIC chipsets provide the ability to switch between several user-provided battery supplies to aid thermal management. Two specific scenarios where this method may be required follow: Ringing to off-hook state transition (Si3220): During the on-hook operating state, the Dual ...
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... Ringing Battery Switch (Si3220 only) Battery Select Indicator Battery Switching LPF *Note: Usable range for BATHTH and BATLTH is limited to the V SVBAT 806 kΩ V BLO V BHI Figure 19. External Battery Switching Using the Si3220/Si3225 Si3220/25 Si3200/02 Register/RAM Register/RAM Mnemonic Bits BATHTH BATHTH[14:7] BATLTH BATLTH[14:7] RLYCON GPO ...
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... Q2 R101 R102 R103 44 using the switch internal to the Si3200/2. The Si3220’s GPO pin is used along with the external transistor circuit to switch the V onto the Si3200/2’s V The GPO signal is driven automatically by the ringing cadence provided that the RRAIL bit of the RLYCON ...
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... Refer to Figure 18 on page 38 for the discrete bipolar transistor references) used in the equation below (Q1, Q2, Q5 and Q6 – note that the Si3200/2 has corresponding MOS transistors). The same I equation applies to the discrete bipolar linefeed as well as the Si3200/2 linefeed device ...
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... LONG in the following equation. Refer to Figure 18 on page 38 for the transistor references used in the equation (Q1, Q2, Q5, and Q6—note that the Si3200/2 has corresponding MOS transistors). The same I equation applies to the discrete bipolar linefeed as well as the Si3200/2 linefeed device. ...
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... Setting” indicate the state initially selected by the host CPU (e.g., TIP-OPEN) and the automatic transition to the FORWARD-ACTIVE state due to a ground key event (when RING is connected to GND). The transition from state #2 to state #3 in Table 27 is the automatic transition from TIP-OPEN to FWD-ACTIVE in response to LCR = 1. Si3220/25 Si3200/ LOOP Rev ...
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... Si3220/25 Si3200/02 Table 27. State Transitions During Ground Key Detection # Loop State 1 LOOP OPEN 2 RING-GND 3 RING-GND (FWD-ACTIVE) 4 LOOP CLOSURE (FWD-ACTIVE) 5 LOOP OPEN (FWD-ACTIVE Input LONG Signal I Processor LFS Figure 22. Ground Key Detection Circuitry 48 LINEFEED I I LOOP LONG State (mA) (mA) LFS = (TIP-OPEN) LFS = 3 22 – ...
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... LONGHITH (enabled) Ground Key Threshold LONGLOTH (released) Ground Key Filter Coefficient LONGLPF *Note: The usable range for LONGHITH and LONGLOTH is limited to 16 mA. Setting a value >16 mA will disable threshold detection. Si3220/25 Si3200/02 Register/RAM Programmable RAM Bits LONGS IRQEN2 LONGE LFS[2:0] Monitor only ...
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... Adding dc offset to the ringing signal decreases the maximum possible ringing amplitude. Adding significant dc offset also increases the power dissipation in the Si3200/2 and may require additional airflow or modified PCB layout to maintain acceptable operating temperatures in the line feed circuitry. The Dual ProSLIC chipset automatically ...
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... Current Sense Ringing Initial Phase RINGPHAS Sinusoidal Trapezoid External Ringing Ringing Relay Driver Enable RELAYCON (Si3225 only) Ringing Overhead Voltage VOVRING Ringing Speedup Timer SPEEDUPR Si3220/25 Si3200/02 Register/RAM Bits TRAP Sinusoid/Trapezoid TAEN Enabled/Disabled TIEN Enabled/Disabled RINGEN Enabled/Disabled RINGTA[15:0] RINGTI[15:0] LF[2:0] VOC ...
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... Si3220/25 Si3200/02 3.12.1. Internal Sinusoidal Ringing A sinusoidal ringing waveform is generated by the on- chip digital tone generator. The tone generator used to generate ringing tones is a two-pole resonator with a programmable frequency and amplitude. Since ringing frequencies are low compared to the audio band signaling frequencies, the sinusoid is generated kHz rate ...
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... RINGCON register. In this mode, the polarity of VOFF must also be reversed (in normal ringing polarity VOFF is subtracted from –80 V, and in reverse polarity, ringing VOFF is added to –80 V). Si3220/25 Si3200/02 3.14. Ringing Coefficients The ringing coefficients are calculated in decimals for sinusoidal and trapezoidal waveforms. The RINGPHAS ...
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... Si3220/25 Si3200/02 3.14.2. External Unbalanced Ringing The Si3225 supports centralized, unbalanced ringing schemes by providing a ringing relay driver as well as inputs from an external ring trip circuit. Using this scheme, line-card designers can use the Dual ProSLIC chipset in architectures with minimal system changes. 3.14.3. Linefeed Overhead Voltage Considerations ...
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... ILOOP Signal Rectifier Processor Figure 27. Ring Trip Detect Processing Circuitry Si3220/25 Si3200/02 mode change (active mode). The ringtrip timeout counter ensures ringing is exited within its time setting (RTCOUNT x 1.25 ms/LSB, typically 200 ms). 3.15.2. Ringtrip Debounce Interval The ac and dc ring trip debounce intervals can be ...
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... Si3220/25 Si3200/02 Table 30. Recommended Values for Ring Trip Registers and RAM Addresses Ringing Ringing DC Method Frequency Offset Added? Yes 16– Internal Yes (Si3220) 33– 16–32 Hz Yes External (Si3225) 33–60 Hz Yes Notes: 1. All calculated values should be rounded to the nearest integer. 2. Refer to Ring Trip Debounce Interval for RTACDB and RTDCDB equations. ...
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... RRDa and RRDb are included for the Si3225 only. In most applications, the relay can be driven directly from the Dual ProSLIC with no external relay drive circuitry required. Figure 28 illustrates the internal relay driver circuitry using relay. Si3220/25 Si3200/ Si3220/ Si3225 ...
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... Si3220/25 Si3200/02 Si3220/ Si3225 Figure 29. Driving Relays with V The maximum allowable R value can be calculated with the following equation: DRV MaxR DRV Table 32. Recommended R ProSLIC V Relay V DD 3.3 V ±5% 3.3 V ± ± ±5% 3.3 V ± ±5% 3.3 V ± ±10% 3.3 V ± ±10% 3.3 V ± ...
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... Si3220/25 Si3200/02 Rev. 1.3 59 ...
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... Si3220/25 Si3200/ OFF RING 510 Ω 806 kΩ 806 kΩ Si3225 Figure 31. Si3225 External Ring Trip Circuitry 3.16.1. Ringing Relay Activation During Zero Crossings The Si3225 is for applications that use a centralized ringing generator and a per-channel ringing relay to connect the ringing signal to the TIP/RING pair. The ...
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... V (V) TIP/RING Figure 32. Wink Function with Programmable Ramp Rate Si3220/25 Si3200/02 A wink function slowly ramps down the TIP-RING voltage (V OC VOC value (set in the VOC RAM location). This scheme lights a message-waiting lamp in certain handsets. No change to the linefeed register is necessary to enable this function ...
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... Si3220/25 Si3200/02 3.18. Two-Wire Impedance Synthesis Two-wire impedance synthesis is performed on-chip to optimally match the output impedance of the Dual ProSLIC to the impedance of the subscriber loop thus minimizing the receive path signal reflected back onto the transmit path. The Dual ProSLIC chipset provides ...
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... During device initialization, steps and 7 should always be performed even if the digital impedance synthesis coefficients are not programmed. Si3220/25 Si3200/02 3.19. Transhybrid Balance Filter The Dual ProSLIC devices provide a transhybrid balance function via a digitally-programmable balance filter block. (See “H” block in Figure 11.) The Dual ...
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... Si3220/25 Si3200/02 8 kHz Clock OSCnEN Zero 16-Bit Cross Modulo OSCnTA Logic Expire Counter OSCnTI Expire OSCnTA OSCnTAEN OSCnTI OSCnTIEN *Tone Generator 1 Only n = "1" or "2" for Tone Generator 1 and 2, respectively 3.20.2. Oscillator Frequency and Amplitude Each of the two tone generators contains a two-pole ...
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... Oscillator 2 Active Timer Oscillator 2 Inactive Timer Oscillator 2 Control Oscillator 2 Interrupts IRQVEC1, IRQEN1 Si3220/25 Si3200/02 Figure example of an output cadence that uses the zero crossing feature. One-shot oscillation is possible with OSC1EN and OSC1TAEN. Direct control over the cadence is achieved by setting the OSC1EN bit directly if OSC1TAEN and OSC1TIEN are disabled ...
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... Si3220/25 Si3200/02 OSC1EN ... ... 0,1 , OSC1TA ENSYNC1 Tone Gen. 1 Signal Output Figure 36. Tone Generator Timing Diagram First Ring Burst Message Message Parameter 1 Type Length Message Header Parameter Type Figure 37. On-Hook Caller ID Transmission Sequence 66 ... ... 0,1 , OSC1TI 0,1 Channel Mark Seizure Packet Parameter 2 Message Body ...
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... FSK 1-0 Transition Freq, High FSK 1-0 Transition Freq, Low *Note: Oscillator 1 active timer range and LSB stage valid only for FSK mode. Si3220/25 Si3200/02 requirements. The register and RAM locations for caller ID generation are listed in Table 37. Caller ID data is entered into the 8-bit FSKDAT register ...
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... Si3220/25 Si3200/02 3.22. Pulse Metering Generation The Si3220 offers an additional tone generator to generate tones above the audio frequency band. This oscillator generates billing tones that are typically 12 kHz or 16 kHz. The generator follows the same algorithm as described in "3.20.1. Tone Generator Architecture" on page 63 with the exception that the sample rate for computation is 64 kHz instead of 8 kHz ...
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... The row results are sorted to determine the strongest row frequency, and the column frequencies are sorted as well. Upon completion of this process, checks are made to determine if the strongest row and column tones constitute a DTMF digit. Si3220/25 Si3200/02 Decimation ADC Filter DAC ...
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... Si3220/25 Si3200/02 Table 40 outlines the hex codes corresponding to the detected DTMF digits. Table 40. DTMF Hex Codes Digit Hex code 1 0x1 2 0x2 3 0x3 4 0x4 5 0x5 6 0x6 7 0x7 8 0x8 9 0x9 0 0xA * 0xB # 0xC A 0xD B 0xE C 0xF D 0x0 3.24. Modem Tone Detection The Dual ProSLIC devices are capable of detecting a ...
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... DRXMUTE bits in the DIGCON register are also available to allow muting of the transmit and receive paths without requiring modifications to the TXGAIN or RXGAIN settings. Si3220/25 Si3200/02 3.25.4. TXEQ/RXEQ Equalizer Blocks The TXEQ and RXEQ blocks (see Figure 11 on page 25) represent 4-tap filters that can be used to equalize the transmit and receive paths, respectively ...
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... Si3220/25 Si3200/02 The receive path transfer function requirement, shown in Figure 8 on page 23, is very similar to the transmit path transfer function. The PCM data rate is 8 kHz; so, no frequencies greater than 4 kHz are digitally-encoded in the data stream. At frequencies greater than 4 kHz, the plot in Figure 8 is interpreted as the maximum ...
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... IRQ0–IRQ3 are cleared following a register read operation. If the interrupt status registers are non-zero, the INT pin remains asserted. Si3220/25 Si3200/02 3.28. SPI Control Interface The control interface to the Dual ProSLIC devices is a 4-wire SPI bus modeled after microcontroller and serial peripheral devices ...
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... Si3220/25 Si3200/02 The control byte has the following structure and is presented on the SDI pin MSB first BRDCST R/W REG/RAM Reserved CID[0] CID[1] CID[2] CID[3] See Table 42 for bit definitions. 7 BRDCST Indicates a broadcast operation that is intended for all devices in the daisy chain. This is only valid for write operations since it would cause contention on the SDO pin during a read ...
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... SDO CS CPU SDI SPI Clock Figure 41. SPI Daisy-Chain Mode Rev. 1.3 Si3220/25 Si3200/02 SDI0 SDI Channel 0 CS SDI1 Dual ProSLIC #1 SDO Channel 1 SCLK SDITHRU SDI2 SDI Channel 2 CS SDI3 Dual ProSLIC #2 SDO Channel 3 SCLK SDITHRU SDI4 SDI14 SDI Channel 14 CS SDI15 ...
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... Si3220/25 Si3200/02 In Figure 42, the CID field is zero. As this field is decremented (in LSB to MSB order), the value decrements for each SDI down the line. The BRDCST, R/W, and REG/RAM bits remain unchanged as the control word passes through the entire chain. The odd SDIs are internal to the device and represent the SDI to SDI_THRU connection between channels of the same device ...
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... SDI CONTROL SDO Figure 46. Register Read Operation via a 16-Bit SPI Port Si3220/25 Si3200/02 move into the data register in the SPI for shifting out during the DATA portion of the SPI transfer. This is the data loaded into the data buffer in response to the previous RAM address read request. Therefore, there is a one-deep pipeline nature to RAM address READ operations ...
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... Si3220/25 Si3200/02 CS SCLK SDI CONTROL SDO Figure 47. RAM Write Operation via an 8-Bit SPI Port CS SCLK SDI CONTROL SDO Figure 48. RAM Read Operation via an 8-Bit SPI Port CS SCLK SDI CONTROL SDO Figure 49. RAM Write Operation via a 16-Bit SPI Port CS SCLK SDI CONTROL SDO Figure 50 ...
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... PCLK_CNT 0 1 DRX DTX HI-Z Figure 51. Example, Timeslot 1, Short FSYNC (TXS/RXS = 1) Si3220/25 Si3200/02 contain a flexible slots. DTX data is high-impedance except for the duration of the 8-bit PCM transmit. DTX returns to high- impedance on the negative edge of PCLK during the LSB or on the positive edge of PCLK following the LSB. ...
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... Si3220/25 Si3200/02 PCLK FSYNC PCLK_CNT 0 1 DRX MSB DTX HI-Z MSB Figure 52. Example, Timeslot 1, Long FSYNC (TXS/RXS = 0) PCLK FSYNC PCLK_CNT 0 1 DRX DTX HI-Z Figure 53. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10) 3.30. PCM Companding The Dual ProSLIC devices support both µ-255 Law (µ- Law) and A-Law companding formats in addition to Linear Data mode ...
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... PCLK FSYNC PCLK_CNT DRX MSB DTX HI-Z MSB Figure 54. 16-Bit Linear Mode Example, Timeslots 1 and 2, Long FSYNC Si3220/25 Si3200/ Rev. 1 LSB HI-Z LSB 81 ...
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... Si3220/25 Si3200/02 Table 43. µ-Law Encode-Decode Characteristics Segment #Intervals X Interval Size Number 256 128 __________________ *Note: Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. 82 Value at Segment Endpoints Digital Code 8159 10000000b . . . 4319 4063 10001111b . . . 2143 2015 10011111b ...
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... Characteristics are symmetrical about analog zero with sign bit = 0 for negative values. 2. Digital code includes inversion of even-numbered bits. Other available formats include inversion of odd bits, inversion of all bits bit inversion. See "3.30. PCM Companding" on page 80 for more details. Si3220/25 Si3200/02 Value at segment endpoints Digital Code ...
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... Si3220/25 Si3200/02 3.31. General Circuit Interface The Dual ProSLIC devices also contain an alternate communication interface to the SPI and PCM control and data interface. The general circuit interface (GCI) is used for the transmission and reception of both control and data information onto a GCI bus. The PCM and GCI interfaces are both four-wire interfaces and share the same pins ...
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... GCI mode. FS SF0 SF1 Sub-Frame Channel Figure 55. Time-Multiplexed GCI Highway Frame Structure Si3220/25 Si3200/02 Table 48. Subframe Selection 16-Bit GCI Mode while the GCI Subframe 0 Selected (Voice channels 0–1) GCI Subframe 1 Selected (Voice channels 2–3) GCI Subframe 2 Selected (Voice channels 4–5) GCI Subframe 3 Selected (Voice channels 6– ...
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... Si3220/25 Si3200/02 FS CH0 Sub-Frame 16 B1 Figure 56. GCI Highway Frame Structure for 16-Bit GCI Mode 1st Byte MX Transm itter MX MR Receiver MR Figure 57. Monitor Handshake Timing 86 125 µ Frame CH1 CH2 C 2nd Byte 3rd Byte ACK ACK 1st Byte 2nd Byte 125 µ ...
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... In this manner, multiple consecutive registers can be read or written in one transmission sequence. Si3220/25 Si3200/02 By correctly manipulating the MX and MR bits, a transmission sequence can continue from the beginning specified address until an invalid memory location is reached ...
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... Si3220/25 Si3200/02 Idle Rec eiv alid New bit calcu lated and tran s m itted on d ata ups tream (D TX) line. MX received d ata dow n s trea lin e. LL: Las t look of m onitor b yte received line. ABT: Abort ind ication to in terna l s ource. ...
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... MX: MX bit calculated and expected line. MXR : MX bit s am pled line. C LS: C ollis ion w ithin the m onitor data byte line. R QT: R eques t for trans ion from internal s ource. ABT: Abort reques t/indication. Figure 59. Dual ProSLIC Monitor Transmitter State Diagram Si3220/25 Si3200/ Wait A bort ...
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... Si3220/25 Si3200/02 Figures 60 and 61 are example timing diagrams of a register read and a register write to the Dual ProSLIC using the GCI. As noted in Figure 59, the transmitter should always anticipate the acknowledgement of the receiver for correct communication with the Dual ProSLIC. Devices that do not accept this “best case” timing scenario will not be able to communicate with the Dual ProSLIC ...
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... Frame MX Downstream Bit MR Downstream Bit Monitor Data Upstream $FF $FF $FF $FF $FF MX Upstream Bit MR Upstream Bit = Acknowledgement of data reception Figure 61. Example Write to Registers $10 and $11 in Channel 0 of the Dual ProSLIC Si3220/25 Si3200/02 $01 $10 $10 Data to be Data to be written to written to $10 $10 $FF $FF $FF ...
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... Si3220/25 Si3200/02 3.31.3. Programming the Dual ProSLIC Using the Monitor Channel The Dual ProSLIC devices use the monitor channel to Transfer status or operating mode information to and from the host processor. Communication with the Dual ProSLIC should be in the following format: Byte 1: Device Address Byte ...
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... Ground Start (Ring Open) Note corresponding to Channel A or Channel B. Si3220/25 Si3200/02 Figure 63 illustrates the transmission protocol for the C/I bits within the downstream SC channel. New data received by either channel must be present and match for two consecutive frames to be considered valid. When a new command is communicated via the ...
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... The transition to the OPEN state stemming from power alarm detection is intended to protect the Dual ProSLIC circuit in the event that too much power is dissipated in the Si3200/2 LFIC. This alarm is typically due to a fault in the application circuit or on the subscriber loop but can be caused by intermittent power spikes depending on the threshold to which the alarm is set ...
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... Ground key information on channel A CI2B Interrupt information on channel B CI1B Hook status information on channel B CI0B Ground key information on channel B Si3220/25 Si3200/02 represent a valid transfer. The upstream C/I bits are defined as follows: CI2A, CI1A, CI0A CI2B, CI1B, CI0B except that the MR, MX Detection/Control Bits Transition ...
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... Si3220/25 Si3200/02 The interrupt information for channels A and single bit that indicates that one or more interrupts might exist on the respective channel. Each of the individual interrupt flags (see registers 18–20) can be individually masked by writing the appropriate bit in registers 21–23 to ignore specific interrupts. When using the GCI mode, ...
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... Tone generation. The Dual ProSLIC devices can generate single or dual tones over the entire audio band and can direct them into either the transmit or receive path depending on the diagnostic requirements. Ringing signals from 4–100 Hz can also be generated. Si3220/25 Si3200/02 Range Accuracy/Resolution Signal Generation Tools 0.875 ...
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... Si3220/25 Si3200/02 VTIP VRING VLOOP VLONG ILOOP ILONG VRING,EXT IRING,EXT Figure 64. SLIC Diagnostic Filter Structure 3.32.4. Measurement Tools 8-Bit monitor A/D converter. This 8-bit A/D converter monitors all dc and low-frequency voltage and current data from TIP to ground and RING to ground. Two additional values, TIP – RING and TIP + RING, are calculated and stored in on-chip registers to analyze metallic and longitudinal effects ...
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... Power measurement is performed by using a single-pole IIR filter to average the output of the sixth-order IIR filter. Si3220/25 Si3200/02 The power averaging filter time constant is absolute value programmable, and the average power result is read from the TESTAVO RAM location. ...
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... Si3220/25 Si3200/02 Line capacitance measurement. Implemented like the ac line impedance measurement test above, but the frequency band of interest is between 1 kHz and 3.4 kHz. Knowing the synthesized two-wire impedance of the Dual ProSLIC, the roll-off effect can be used to calculate the ac line capacitance. Ringing voltage verification. Verifies that the ...
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... Pin Number(s) Si3220 Si3225 SVBATa SVBATb RPOa, RPOb 2,15 2,15 RPIa RPIb RNIa RNIb RNOa, RNOb CAPPa CAPPb CAPMa CAPMb QGND 8 8 Si3220/25 Si3200/ GPOa SVBATa RPOa 2 46 SDITHRU RPIa 3 45 SDI RNIa 4 44 SDO RNOa 5 43 SCLK CAPPa 6 42 VDD4 ...
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... Analog current output drives dc current onto RING side of sub- scriber loop in reverse polarity. Also modulates ac current onto RING side of loop. I Temperature Sensor. Senses Internal temperature of Si3200/2. Connect to THERM pin of Si3200 Test Relay Driver Output. Drives test relays for connecting loop test equipment. ...
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... INT 43 43 SCLK 44 44 SDO 45 45 SDI Si3220/25 Si3200/02 Input/ Description Output No Internal Connection. Leave unconnected or connect to ground plane. I External Ring Trip Sensing Input. Used to sense ring-trip condition when using centralized ring generator. Connect to low side of ring sense resistor. O Test Relay Driver Output. ...
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... Si3220/25 Si3200/02 Symbol Pin Number(s) Si3220 Si3225 46 46 SDITHRU BLKRNG epad epad GND 104 Input/ Description Output O Serial Data Daisy Chain. Enables multiple devices to use a single CS for serial port con- trol. Connect SDITHRU pin from master device to SDI pin of slave device. An internal pullup resistor holds this pin high dur- ing idle periods ...
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... RING Output. Connect to the RING lead of the subscriber loop. Operating Battery Voltage. Si3200/2 internal system battery supply. Connect SVBATa/b pin from Si3220/25 and decouple with a 0.1 µF/100 V filter capacitor. High Battery Voltage. Connect to the system ringing battery supply. Decouple with a 0.1 µF/100 V filter capacitor ...
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... Si3220/25 Si3200/02 Pin #(s) Symbol Input/ Output 12 IRINGN I 13 IRINGP I 14 THERM O 15 ITIPN I 16 ITIPP I epad GND 106 Description Negative RING Current Control. Connect to the IRINGN lead of the Si3220 or Si3225. Positive RING Current Drive. Connect to the IRINGP lead of the Si3220 or Si3225. ...
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... All dimensions are shown in millimeters unless otherwise noted. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. This package outline conforms to JEDEC MS-026, variant ACD-HD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Si3220/25 Si3200/02 Figure 65. 64-Pin Exposed Pad TQFP Table 53. Package Dimensions Symbol Max 1 ...
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... Si3220/25 Si3200/02 7. Package Outline: 16-Pin ESOIC Figure 66 illustrates the package details for the Si3200/2. Table 54 lists the values for the dimensions shown in the illustration Seating Plane Figure 66. 16-Pin Thermal Enhanced Small Outline Integrated Circuit (ESOIC) Package Table 54. Package Diagram Dimensions 108 ...
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... Si322x Dual ProSLIC Demo PBX and GR-909 Testing Software Guide” “AN86: Ringing / Ringtrip Operation and Architecture on the Si3220/Si3225” “AN88: Dual ProSLIC Line Card Design” “AN91: Si3200 Power Offload Circuit” Si3220PPT0-EVB Data Sheet Si3225PPT0-EVB Data Sheet Note: Refer to www.silabs.com for a current list of support documents for this chipset. ...
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... Si3220/25 Si3200/02 9. Dual ProSLIC Selection Guide Part Number Description Si3200-X-FS 100 V Linefeed IC Si3200-X-GS 100 V Linefeed IC Si3202-X-FS 125 V Linefeed IC Si3202-X-GS 125 V Linefeed IC Si3220-X-FQ Dual ProSLIC Si3220-X-GQ Dual ProSLIC Si3225-X-FQ Dual ProSLIC Si3225-X-GQ Dual ProSLIC Notes: 1. “X” denotes product revision. 2. Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. ...
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... Added note to Tables 15 and 17 to clarify SDO and DTX pulldown requirements when multiple Si3220/25s are connected to the same SPI or PCM bus. Updated "9. Dual ProSLIC Selection Guide" on page 110. Revision 1.2 to Revision 1.3 Added Si3202 125 V linefeed IC. Si3220/25 Si3200/02 Rev. 1.3 111 ...
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... Si3220/25 Si3200/ ONTACT NFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: ProSLICinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...