SI3200-G-GS Silicon Laboratories Inc, SI3200-G-GS Datasheet - Page 80

• Manufacturer Part Number: SI3200-G-GS
• Description: SLIC 2-CH 63dB 45mA 3.3V 6-Pin SMD
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3200-G-GS

• Package: 6SMD
• Number Of Channels Per Chip: 2
• Polarity Reversal: Yes
• Longitudinal Balanced: 63 dB
• Loop Current: 45 mA
• Minimum Operating Supply Voltage: 3.13 V
• Typical Operating Supply Voltage: 3.3 V
• Typical Supply Current: 0.11 mA
• Function: Subscriber Line Interface Concept (SLIC), CODEC
• Interface: GCI, PCM, SPI
• Number Of Circuits: 2
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 110µA
• Power (watts): 941mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Includes: Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si3220/25 Si3200/02
3.30. PCM Companding
The Dual ProSLIC devices support both µ-255 Law (µ-
Law) and A-Law companding formats in addition to
Linear Data mode. The data format is selected via the
PCMF bits of the PCM Mode Select register. µ-Law
mode is more commonly used in North America and
Japan, and A-Law is primarily used in Europe and other
countries. These 8-bit companding schemes follow a
segmented curve formatted as a sign bit (MSB) followed
by three chord bits and four step bits. A-Law typically
uses a scheme of inverting all even bits while µ-Law
does not. Dual ProSLIC devices also support A-Law
with inversion of even bits, inversion of all bits, or no bit
inversion by programming the ALAW bits of the PCM
Mode Select register to the appropriate setting.
80
PCLK_CNT
PCLK_CNT
Figure 53. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10)
FSYNC
FSYNC
PCLK
DRX
DTX
PCLK
DRX
DTX
Figure 52. Example, Timeslot 1, Long FSYNC (TXS/RXS = 0)
HI-Z
HI-Z
0
0
MSB
MSB
1
1
2
2
3
3
4
4
5
5
6
6
Rev. 1.3
7
7
8
Table 43 on page 82 and Table 44 on page 83 define
the µ-Law and A-Law encoding formats.
The Dual ProSLIC devices also support a 16-bit linear
data format with no companding. This Linear mode is
typically used in systems that convert to another
companding format, such as adaptive differential PCM
(ADPCM) or systems that perform all companding in an
external DSP. The data format is 2s complement with
MSB first (sign bit). Transmitting and receiving data via
Linear mode requires two continuous time slots. An 8-bit
Linear mode enables 8-bit transmission without
companding.
LSB
LSB
8
9
9
10
10
11
MSB
MSB
11
12
12
13
HI-Z
13
14
14
15
15
16
16
17
17
18
LSB
LSB
18
HI-Z