SI3200-G-GS Silicon Laboratories Inc, SI3200-G-GS Datasheet - Page 65

• Manufacturer Part Number: SI3200-G-GS
• Description: SLIC 2-CH 63dB 45mA 3.3V 6-Pin SMD
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3200-G-GS

• Package: 6SMD
• Number Of Channels Per Chip: 2
• Polarity Reversal: Yes
• Longitudinal Balanced: 63 dB
• Loop Current: 45 mA
• Minimum Operating Supply Voltage: 3.13 V
• Typical Operating Supply Voltage: 3.3 V
• Typical Supply Current: 0.11 mA
• Function: Subscriber Line Interface Concept (SLIC), CODEC
• Interface: GCI, PCM, SPI
• Number Of Circuits: 2
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 110µA
• Power (watts): 941mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Includes: Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To enable automatic cadence for tone generator 1,
define the OSC1TA and OSC1TI registers and set the
OSC1TAEN and OSC1TIEN bits. This enables each of
the timers to control the state of the oscillator enable bit,
OSC1EN. The 16-bit counter counts until the active
timer expires, at which time the 16-bit counter resets to
zero and begins counting until the inactive timer
expires. The cadence continues until the user clears the
OSC1TA and OSC1TIEN control bits. Setting the
ZEROEN1 bit implements the zero crossing detect
feature. This ensures that each oscillator pulse ends
without a dc component. The timing diagram in
Oscillator 1 Frequency
Coefficient
Oscillator 1 Amplitude Coeffi-
cient
Oscillator 1 Initial Phase
Coefficient
Oscillator 1 Active Timer
Oscillator 1 Inactive Timer
Oscillator 1 Control
Oscillator 1 Interrupts
Oscillator 2 Frequency
Coefficient
Oscillator 2 Amplitude Coeffi-
cient
Oscillator 2 Initial Phase
Coefficient
Oscillator 2 Active Timer
Oscillator 2 Inactive Timer
Oscillator 2 Control
Oscillator 2 Interrupts
Parameter
Parameter
Table 35. Register and RAM Locations Used for Tone Generation
IRQVEC1, IRQEN1 OS1TAS, OS1TIS, OS1TAE,
IRQVEC1, IRQEN1
O2TALO/O2TAHI
O1TALO/O1TAHI
OMODE, OCON
OMODE, OCON
O2TILO/O2TIHI
O1TILO/O1TIHI
Register/RAM
Mnemonics
OSC1FREQ
OSC2FREQ
OSC1PHAS
OSC2PHAS
OSC1AMP
OSC2AMP
Location
Tone Generator 1
Tone Generator 2
Rev. 1.3
Register/RAM Address
ENSYNC2, OSC2TAEN,
ENSYNC1, OSC1TAEN,
Figure 36 is an example of an output cadence that uses
the zero crossing feature.
One-shot oscillation is possible with OSC1EN and
OSC1TAEN. Direct control over the cadence is
achieved by setting the OSC1EN bit directly if
OSC1TAEN and OSC1TIEN are disabled.
The operation of tone generator 2 is identical to that of
tone generator 1 using its respective control registers.
Note: Tone Generator 2 should not be enabled simulta-
FSKSSEN, OSC1FSK,
OSC1TIEN, OSC1EN
OSC2TIEN, OSC2EN
ZEROEN1, ROUT1,
ZEROEN2, ROUT2,
Register/RAM Bits
OS2TAS, OS2TIS,
OSC1FREQ[15:3]
OSC2FREQ[15:3]
OS2TAE, OS2TIE
OSC1PHAS[15:0]
OSC2PHAS[15:0]
OSC1AMP[15:0]
OSC2AMP[15:0]
OSC2TA[15:0]
OSC1TA[15:0]
OSC1TI[15:0]
OSC2TI[15:0]
neously with the ringing oscillator because of resource
sharing within the hardware.
OS1TIE
Si3220/25 Si3200/02
Sets oscillator frequency
Sets oscillator amplitude
Sets oscillator frequency
Sets oscillator amplitude
Enables all Oscillator 1
Enables all Oscillator 2
Interrupt enable/status
Interrupt enable/status
Description/Range
Description/Range
0 to 8.19 s (125 µs)
0 to 8.19 s (125 µs)
0 to 8.19 s (125 µs)
0 to 8.19 s (125 µs)
Sets initial phase
Sets initial phase
(default = 0)
(default = 0)
parameters
parameters
(LSB Size)
65