SI3018-F-FT Silicon Laboratories Inc, SI3018-F-FT Datasheet - Page 57
![no-image](/images/manufacturer_photos/0/6/609/silicon_laboratories_inc_sml.jpg)
SI3018-F-FT
Manufacturer Part Number
SI3018-F-FT
Description
IC VOICE DAA GCI/PCM/SPI 16TSSOP
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI3018-F-FT.pdf
(112 pages)
Specifications of SI3018-F-FT
Function
Data Access Arrangement (DAA)
Interface
Serial
Number Of Circuits
1
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
8.5mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Includes
Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI3018-F-FT
Manufacturer:
SiliconL
Quantity:
960
5.45. Receive SC Channel
:
These bits are defined as follows:
CIR6: Reserved
CIR5: Reserved
CIR4: ONHM
CIR3: TGDE
CIR2: RG
CIR1: OH
Data that is received must be consistent and match for
at least two consecutive frames to be considered valid.
When a new command or status is communicated via
the C/I bits, the data must be sent for at least two
consecutive frames to be recognized by the Si3050.
The following steps describe the protocol of how C/I bits
are stored, detected, and validated. This is illustrated in
Figure 47.
1. The current state of the C/I bits are stored in a
2. Upon receipt of an SC channel with C/I bits that differ
3. The C/I bits in the SC channel received in the frame
MSB
primary register P. If the received C/I bits are
identical to this current state, no action is taken.
from the current state, these new C/I bits are
immediately latched into a secondary register S.
immediately after the SC channel just stored in S are
compared with the C/I bits in the S register.
a. If the C/I bits in these two channels are identical,
b. If a set of C/I bits is latched into the S register
c. If the C/I bits in the SC channel received
then the C/I bits in the S register are loaded into
the P register and are considered a valid change
of C/I bits. The Si3050 then responds accordingly
to the changed C/I bits.
and the subsequent set of C/I bits received does
not match either the S or P registers, then the
newly received set of C/I bits are latched into the
S register. This continues to occur as long as the
subsequent set of C/I bits received differs from
the C/I bits in the S and P registers.
immediately after the SC channel just stored in S
do not match the C/I bits stored in S, but DO
match the C/I bits stored in P, then the single set
of C/I bits stored in the S latch are invalidated,
and the current state of the C/I bits in P remains
unchanged.
CIR6
7
CIR5
6
CIR4
5
CIR3
4
Rev. 1.2
C/I Bits
CIR2
3
CIR1
2
MR
1
Si3050
MX
0
LSB
57