MAX2991ECM+ Maxim Integrated Products, MAX2991ECM+ Datasheet - Page 14

• Manufacturer Part Number: MAX2991ECM+
• Description: IC TXRX FRONT-END 48LQFP
• Manufacturer: Maxim Integrated Products
• Type: General Purposer

Specifications of MAX2991ECM+

• Function: Analog Front-End Transceiver
• Interface: SPI Serial
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 36mA, 70mA
• Power (watts): 1.54W
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Includes: Automatic Gain Control (AGC)
• Product: Analog Front End
• Data Rate: 1.2 Msps
• Interface Type: Digital
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current: 36 mA, 70 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Maximum Power Dissipation: 1535 mW
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power-Line Communications (PLC) Integrated
Analog Front-End Transceiver
Address 0x01: Tx Configuration (TXCONF<15:0>), Default: 0x282B
Address 0x03: Process Tuner Configuration (PTUN1<5:0>), Default: 0x13
14
OVERWRT_NDGE
TXLPFBW<1:0>
TXCONV_EDGE
PREDRVGAIN
TXDATA_DLY
_____________________________________________________________________________________
PREDRDYN
PTCLKMUX
BIT NAME
BIT NAME
ENTXBEN
<3:0>
—
—
—
—
LOCATION
LOCATION
(0 = LSB)
(0 = LSB)
12–8
7, 6
1, 0
4, 3
4–1
13
14
15
0
5
2
5
DEFAULT
DEFAULT
01000
0101
00
11
10
1
1
1
0
0
0
0
Active high. Set to 1 to enable the power down of the transmit path.
The transmit path is normally powered down in receive mode.
Predriver gain settings:
0000: Gain = -10dB
0001: Gain = -8dB
0010: Gain = -6dB
0011: Gain = -4dB
0100: Gain = -2dB
0101: Gain = 0dB
0110: Gain = 2dB
0111: Gain = 4dB
1000: Gain = 6dB
Reserved
Transmit lowpass filter mode selection.
00: CENELEC A
01: Narrowband
10: FCC and ARIB
11: Full band
Reserved
Active high. Enables the dynamic control of the predriver gain set
by the command bits C<3:0> in the Tx transmit frame.
Defines the active TXCLK edge used to sample the TXCONV input
(0 = falling edge, 1 = rising edge).
Defines the position of the first TXDATA bit relative to the TXCONV
active edge (0 = first TXDATA bit is coincident with the first active
TXCONV cycle, 1 = first TXDATA bit is one cycle after the first
active TXCONV cycle).
Reserved
Active high. Enables direct programming of process tuner settings
from SPI registers. Set to 0 to enable systematic adjustment of the
process tuner code by PTUNERXADJ and PTUNETXADJ indepen-
dently for Rx and Tx filters, respectively.
Process tuner clock selection:
00 or 01: REFCLK
10: RXCLK
11: TXCLK
Reserved
FUNCTION
FUNCTION