DS2180AN Maxim Integrated Products, DS2180AN Datasheet
DS2180AN
Specifications of DS2180AN
Related parts for DS2180AN
DS2180AN Summary of contents
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... Receive error detection and counting for transmission performance monitoring 5V supply, low-power CMOS technology Surface-mount package available, designated DS2180AQ Industrial temperature range of - +85 C available, designated DS2180AN or DS2180AQN Compatible to DS2186 Transmit Line Interface, DS2187 Receive Line Interface, DS2188 Jitter Attenuator, DS2175 T1/CEPT Elastic Store, DS2290 T1 Isolation Stik, and ...
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DESCRIPTION The DS2180A is a monolithic CMOS device designed to implement primary rate (1.544 MHz) T-carrier transmission systems. The 193S framing mode is intended to support existing Ft/Fs applications (12 frames/superframe). The 193E framing mode supports the extended superframe format ...
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TRANSMIT PIN DESCRIPTION (40-PIN DIP ONLY) Table 1 PIN SYMBOL TYPE 1 TMSYNC I 2 TFSYNC I 3 TCLK I 4 TCHCLK O 5 TSER I 6 TMO O 7 TSIGSEL O 8 TSIGFR O 9 TABCD I 10 TLINK ...
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POWER AND TEST PIN DESCRIPTION (40-PIN DIP ONLY) Table 3 PIN SYMBOL TYPE TEST RECEIVE PIN DESCRIPTION (40-PIN DIP ONLY) Table 4 PIN SYMBOL TYPE 21 RYEL 0 22 RLINK ...
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REGISTER SUMMARY Table 5 REGISTER ADDRESS T/R RSR 0000 RIMR 0001 BVCR 0010 ECR 0011 3 CCR 0100 T/R 3 RCR 0101 3 TCR 0110 TIR1 0111 TIR2 1000 TIR3 1001 TTR1 1010 TTR2 1011 TTR3 1100 RMR1 1101 RMR2 ...
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All data transfers are terminated if the tri-stated when is high. CS DATA I/O Following the eight SCLK cycles that input an address/ command byte to write, a data byte is strobed into the addressed register on the rising edges ...
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ACB: ADDRESS COMMAND BYTE Figure 4 (MSB) - FRSR2 EYELMD SYMBOL POSITION - CCR.7 FRSR2 CCR.6 EYELMD CCR.5 FM CCR.4 SYELMD CCR.3 B8ZS CCR.2 B7 CCR.1 LPBK CCR.0 LOOPBACK (Refer to Figure 4) Enabling loopback will typically induce an out-of-frame ...
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B8ZS The DS2180A supports existing and emerging zero suppression formats. Selection of B8ZS coding maintains system 1’s density requirements without disturbing data integrity as required in emerging clear channel applications. B8ZS coding replaces eight consecutive outgoing 0's with a B8ZS ...
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TRANSMIT SIGNALING When enabled (via TCR.4) channel signaling is inserted in frames 6 and 12 (193S frames 6, 12 and 24 (193E) in the 8 bit position of every channel word. Signaling data is sampled at ...
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TRANSMIT INSERTION HIERARCHY Figure DS2180A ...
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TRANSMIT MULTIFRAME TIMING Figure 9 NOTES: 1. Transmit frame and multiframe timing may be established in one of four ways: a. With TFSYNC tied low, TMSYNC may be pulsed high once every multiframe period to establish multiframe boundaries, allowing ...
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TRANSMIT MULTIFRAME TIMING Figure 10 NOTES: 1. Transmit frame and multiframe timing may be established in one of four ways: a. With TFSYNC tied low, TMSYNC may be pulsed high once every multiframe period to establish multiframe boundaries, allowing ...
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TRANSMIT MULTIFRAME BOUNDARY TIMING Figure 11 NOTES: 1. TLINK timing shown is for 193E framing; in 193E framing, TLINK is sampled as indicated for insertion into F-bit position of odd frames. When S-bit insertion is enabled in 193S, TLINK is ...
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RECEIVE CONTROL REGISTER Figure 12 (MSB) ARC OOF SYMBOL POSITION ARC RCR.7 OOF RCR.6 RCI RCR.5 RCS RCR.4 SYNCC RCR.3 SYNCT RCR.2 SYNCE RCR.1 RESYNC RCR.0 RECEIVE CODE INSERTION Incoming receive channels can be replaced with idle (7F Hex) or ...
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RECEIVE SIGNALING Robbed bit signaling data is presented at RABCD during each channel time in signaling frames for all 24 incoming channels. Logical combination of clocks RMSYNC, RSIGFR and RSIGSEL allow the user to identify and extract AB or ABCD ...
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RECEIVE MULTIFRAME TIMING Figure 15 NOTES: 1. Signaling data is updated during signaling frames on channel boundaries. RABCD outputs the LSB of each channel word in non-signaling frames. 2. RLINK data (FDL-bit) is updated one bit time prior to ...
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RECEIVE MULTIFRAME BOUNDARY TIMING Figure 16 NOTES: 1. RLINK timing is shown for 193E; in 193S, RLINK is updated on even frame boundaries and is held across multiframe edges. 2. Total delay from RPOS and RNEG to RSER output is ...
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RSR: RECEIVE STATUS REGISTER Figure 17 (MSB) BVCS ECS RYEL SYMBOL POSITION BVCS RSR.7 ECS RSR.6 RYEL RSR.5 RCL RSR.4 FERR RSR.3 B8ZSD RSR.2 RBL RSR.1 RLOS RSR.0 RECEIVE ALARM REPORTING Incoming serial data is monitored by the transceiver for ...
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RIMR: RECEIVE INTERRUPT MASK REGISTER Figure 18 (MSB) BVCS ECS RYEL SYMBOL POSITION BVCS RIMR.7 ECS RIMR.6 RYEL RIMR.5 RCL RIMR.4 FERR RIMR.3 B8ZSD RIMR.2 RBL RIMR.1 RLOS RIMR.0 ALARM COUNTERS The three onboard alarm event counters allow the transceiver ...
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BVCR: BIPOLAR VIOLATION COUNT REGISTER Figure 19 (MSB) BVD7 BVD6 BVD5 SYMBOL POSITION BVD7 BVCR.7 BDV0 BVCR.0 This 8-bit binary up counter saturates at 255 and will generate an interrupt for each occurrence of a bipolar violation once saturated (RIMR.7=1). ...
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RYEL OUTPUT The yellow alarm output transitions high when a yellow alarm is detected. A high-low transition indicates the alarm condition has been cleared. The RYEL bit (RSR. “latched” version of the RYEL output. In 193E framing, the ...
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RLOS transitions high during the F-bit time that caused an OOF event (any two of four consecutive F or FPS bits are in error) if auto-resync mode is selected (RCR.1=0). Resync will also occur when T loss of carrier ...
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T1 OVERVIEW Framing Standards The DS2180A is compatible with the existing Bell System D4 framing standard described in ATT PUB 43801 and the new extended superframe format (ESF) as described in ATT C.B. #142. In this document, D4 framing is ...
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FRAMING FORMAT Table 7 FRAME F-BIT USE 1 2 NUMBER FPS FPL CRC ...
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FRAMING FORMAT Table 8 FRAME F-BIT USE 1 2 NUMBER ...
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The bipolar coder also supports the onboard loopback feature. Input-to-output delay of the transmitter is 10 TCLK cycles. RECEIVE SIDE OVERVIEW Synchronizer The heart of the receiver is ...
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CCR.3–YELMD–is equal to a 1). In this mode, F and F patterns must be correctly identified by the synchronizer before sync is declared. Clearing RCR.3 S causes the synchronizer to search for F sync will be ...
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PROCESSOR-BASED TRANSMIT SIGNALING INSERTION Figure 23 PROCESSOR-BASED SIGNALING Many robbed-bit signaling applications utilize a microprocessor to insert transmit signaling data into the out-going data stream. The circuit shown in Figure 23 “decouples” the processor timing from that of the DS2180A ...
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ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the ...
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AC ELECTRICAL CHARACTERISTICS PARAMETER SDI to SCLK Setup SCLK to SDI Hold SDI to SCLK Falling Edge SCLK Low Time SCLK High Time SCLK Rise and Fall Time to SCLK Setup CS SCLK to Hold CS Inactive Time CS 2 ...
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SERIAL PORT READ AC TIMING NOTE: 1. Serial port write must precede a port read to provide address information. AC ELECTRICAL CHARACTERISTICS PARAMETER TCLK Period TCLK Pulse Width TCLK, RCLK Raise & Fall Times TSER, TABCD, TLINK Setup to TCLK ...
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AC ELECTRICAL CHARACTERISTICS PARAMETER Propagation Delay RCLK to RMSYNC, RFSYNC, RSIGSEL, RSIGFR, RLCLK, RCHCLK Propagation Delay RCLK to RSER, RABCD, RLINK Transition Time All Outputs RCLK Period RCLK Pulse Width RCLK Rise and Fall Times RPOS, RNEG Setup to RCLK ...
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TRANSMIT AC TIMING DIAGRAM RECEIVE AC TIMING DIAGRAM DS2180A ...
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DS2180A SERIAL T1 TRANSCEIVER (600 MIL DIP) DIM INCHES MIN MAX 2.050 2.075 0.530 0.550 0.140 0.160 0.600 0.625 0.015 0.040 0.120 0.145 0.090 0.110 0.625 0.675 0.008 0.012 0.015 ...
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DS2180AQ SERIAL T1 TRANSCEIVER (PLCC) DIM CH1 INCHES MIN MAX 0.165 0.180 0.090 0.120 0.020 - 0.026 0.033 0.013 0.021 0.009 0.012 0.042 0.048 0.685 0.695 ...