DS21Q50L Maxim Integrated Products, DS21Q50L Datasheet - Page 25

• Manufacturer Part Number: DS21Q50L
• Description: IC TRANSCEIVER E1 QUAD 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q50L

• Function: Transceiver
• Interface: E1
• Number Of Circuits: 4
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 230mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: AIS Alarms Detector and Generator, Loopback Functions, PRBS Generator / Detector, Remote Detector and Generator
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -

4.1 Power-Up Sequence
On power-up and after the supplies are stable, the DS21Q50 should be configured for operation by
writing to all of the internal registers (this includes setting the test registers to 00h) since the contents of
the internal registers cannot be predicted on power-up. The LIRST (CCR5.4) should be toggled from 0 to
1 to reset the line interface circuitry (it takes the device about 40ms to recover from the LIRST bit being
toggled). Finally, after the SYSCLK input is stable, the ESR bits (CCR4.5 and CCR4.6) should be
toggled from a 0 to 1 (this step can be skipped if the elastic store is disabled).
Register Name:
Register Description:
Register Address:
Bit
Name
RESYNC
SYNCE
NAME
RSMF
RESE
RSIO
RSM
FRC
—
RSMF
7
BIT
7
6
5
4
3
2
1
0
RSM
RSYNC Multiframe Function. Only used if the RSYNC pin is programmed in the
multiframe mode (RCR.6 = 1).
0 = RSYNC outputs CAS multiframe boundaries
1 = RSYNC outputs CRC4 multiframe boundaries
RSYNC Mode Select.
0 = frame mode (See the timing diagrams in Section 19.1.)
1 = multiframe mode (See the timing diagrams in Section 19.1.)
RSYNC I/O Select. (Note: This bit must be set to 0 when RCR .4 = 0).
0 = RSYNC is an output (depends on RCR.6)
1 = RSYNC is an input (only valid if elastic store enabled)
Receive Elastic Store Enable
0 = elastic store is bypassed
1 = elastic store is enabled
Unused. Should be set = 0 for proper operation
Frame Resync Criteria
0 = resync if FAS received in error three consecutive times
1 = resync if FAS or bit 2 of non-FAS is received in error three consecutive times
Sync Enable
0 = auto resync enabled
1 = auto resync disabled
Resync. When toggled from low to high, a resync is initiated. Must be cleared and
set again for a subsequent resync.
6
RCR
Receive Control Register
10 Hex
RSIO
5
RESE
4
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—
FUNCTION
3
FRC
2
SYNC
1
RESYNC
0