FT2232HQ - REEL FTDI, Future Technology Devices International Ltd, FT2232HQ - REEL Datasheet - Page 13

• Manufacturer Part Number: FT2232HQ - REEL
• Description: IC USB UART/FIFO DUAL HS 64-QFN
• Manufacturer: FTDI, Future Technology Devices International Ltd
• Series: USBmadeEZ-FIFOr

Specifications of FT2232HQ - REEL

• Features: USB to UART and/or FIFO, SPI, I2C, JTAG
• Number Of Channels: 2, DUART
• Fifo's: 4096 Byte
• Protocol: RS-232, RS-422, RS-485
• Voltage - Supply: 3 V ~ 3.6 V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 64-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 768-1025-2; FT2232HQ - REEL

3.4.3 FT2232H pins used in an FT245 Style Asynchronous FIFO Interface
The FT2232H channel A or channel B can be configured as a FT245 asynchronous FIFO interface. When
configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.6. To
enter this mode the external EEPROM must be set to make port A or B or both 245 mode. In this mode,
data is written or read on the falling edge of the RD# or WR# signals.
24,23,22,21,
Table 3.6 Channel A and Channel B FT245 Style Asynchronous FIFO Configured Pin Descriptions
19,18,17,16
Channel A
Pin No.
26
27
28
29
30
46,45,44,43,
41,40,39,38
Channel B
Pin No.
48
52
53
54
55
Copyright © 2010 Future Technology Devices International Limited
Channel A =
ADBUS[7:0]
Channel B =
BDBUS[7:0]
FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC
Name
RXF#
TXE#
SIWU
WR#
RD#
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
Type
I/O
D7 to D0 bidirectional FIFO data. This bus is normally input
unless RD# is low.
When high, do not read data from the FIFO. When low,
there is data available in the FIFO which can be read by
driving RD# low. When RD# goes high again RXF# will
always go high and only become low again if there is
another byte to read. During reset this signal pin is tri-
state, but pulled up to VCCIO via an internal 200kΩ
resistor.
When high, do not write data into the FIFO. When low, data
can be written into the FIFO by strobing WR# high, then
low. During reset this signal pin is tri-state, but pulled up to
VCCIO via an internal 200kΩ resistor.
Enables the current FIFO data byte to be driven onto
D0...D7 when RD# goes low. Fetches the next FIFO data
byte (if available) from the receive FIFO buffer when RD#
goes high.
Writes the data byte on the D0...D7 pins into the transmit
FIFO buffer when WR# goes from high to low.
The Send Immediate / WakeUp signal combines two
functions on a single pin. If USB is in suspend mode
(PWREN# = 1) and remote wakeup is enabled in the
EEPROM , strobing this pin low will cause the device to
request a resume on the USB Bus. Normally, this can be
used to wake up the Host PC.
During normal operation (PWREN# = 0), if this pin is
strobed low any data in the device TX buffer will be sent out
over USB on the next Bulk-IN request from the drivers
regardless of the pending packet size. This can be used to
optimize USB transfer speed for some applications. Tie this
pin to VCCIO if not used. (Also see note 1, 2, 3 in section
4.12)
FT245 Configuration Description
Document No.: FT_000061
Clearance No.: FTDI#77
Datasheet Version 2.10
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