LTC4280IUFD#TR Linear Technology, LTC4280IUFD#TR Datasheet - Page 20

• Manufacturer Part Number: LTC4280IUFD#TR
• Manufacturer: Linear Technology

Specifications of LTC4280IUFD#TR

• Lead Free Status / Rohs Status: Supplier Unconfirmed

LTC4280
APPLICATIONS INFORMATION
Digital Interface
The LTC4280 communicates with a bus master using a
2-wire interface compatible with I
I
The LTC4280 is a read-write slave device and supports
SMBus bus Read Byte, Write Byte, Read Word and Write
Word commands. The second word in a Read Word
command is identical to the fi rst word. The second word
in a Write Word command is ignored. Data formats for
these commands are shown in Figures 6 to 11.
START and STOP Conditions
When the bus is idle, both SCL and SDA are high. A bus
master signals the beginning of a transmission with a start
condition by transitioning SDA from high to low while SCL
is high, as shown in Figure 6. When the master has fi nished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
20
2
C extension for low power devices.
SDA
SCL
CONDITION
START
S
ADDRESS
a6 - a0
1 - 7
2
C Bus and SMBus, an
R/W
8
Figure 6. Data Transfer Over I
ACK
9
1 - 7
b7 - b0
DATA
I
Twenty-seven distinct bus addresses are available using
three 3-state address pins, ADR0-ADR2. Table 1 shows
the correspondence between pin states and addresses.
Note that address bits B7 and B6 are internally confi gured
to 10. In addition, the LTC4280 responds to two special
addresses. Address (1011 111) is a mass write address
that writes to all LTC4280s, regardless of their individual
address settings. Mass write can be disabled by setting
register A4 to zero. Address (0001 100) is the SMBus Alert
Response Address. If the LTC4280 is pulling low on the
ALERT pin, it acknowledges this address by broadcasting
its address and releasing the ALERT pin.
Acknowledge
The acknowledge signal is used in handshaking between
transmitter and receiver to indicate that the last byte of
data was received. The transmitter always releases the
SDA line during the acknowledge clock pulse. When the
slave is the receiver, it pulls down the SDA line so that it
2
8
C Device Addressing
2
C or SMBus
ACK
9
1 - 7
b7 - b0
DATA
8
ACK
9
CONDITION
STOP
P
4280 F06
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